hdpdeps.ref

xilinx环境下开发vhdl语言串行接口设计

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FL E:/aa/ctrl.vhdl 2008/10/31.15:10:16
FL E:/aa/bps.vhdl 2008/10/31.13:43:10
FL d:/xilinxise6.2/aa/rev.vhdl 2008/10/29.23:49:04
FL D:/aa/bps.vhdl 2008/10/31.00:04:36
FL F:/aa/ctrl.vhdl 2008/10/31.16:45:42
EN work/CTRL            FL F:/aa/ctrl.vhdl PB ieee/STD_LOGIC_1164 \
      PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/CTRL/MAIN       FL F:/aa/ctrl.vhdl EN work/CTRL
FL F:/aa/bps.vhdl 2008/10/31.17:06:48
EN work/BPS             FL F:/aa/bps.vhdl PB ieee/STD_LOGIC_1164 \
      PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/BPS/MAIN        FL F:/aa/bps.vhdl EN work/BPS
FL e:/aa/bps.vhdl 2008/10/31.00:06:06
FL E:/aa/rev.vhdl 2008/10/31.00:06:14
FL D:/aa/rev.vhdl 2008/10/30.21:05:28
FL F:/aa/xmit.vhdl 2008/10/31.00:06:16
EN work/XMIT            FL F:/aa/xmit.vhdl PB ieee/STD_LOGIC_1164 \
      PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/XMIT/MAIN       FL F:/aa/xmit.vhdl EN work/XMIT
FL e:/aa/ctrl.vhdl 2008/10/31.14:13:32
FL F:/aa/rev.vhdl 2008/10/31.15:36:26
EN work/REV             FL F:/aa/rev.vhdl PB ieee/STD_LOGIC_1164 \
      PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/REV/MAIN        FL F:/aa/rev.vhdl EN work/REV
FL f:/aa/serial.vhdl 2008/10/31.16:54:54
EN work/SERIAL          FL f:/aa/serial.vhdl PB ieee/STD_LOGIC_1164 \
      PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/SERIAL/BEHAVIORAL FL f:/aa/serial.vhdl EN work/SERIAL CP BPS          CP XMIT \
      CP REV            CP CTRL
FL F:/aa/serial.vhdl 2008/10/31.16:54:18