aa.npl.bak

xilinx环境下开发vhdl语言串行接口设计

JDF G
// Created by Project Navigator ver 1.0
PROJECT aa
DESIGN aa
DEVFAM virtex2
DEVFAMTIME 1225368784
DEVICE xc2v2000
DEVICETIME 1225368784
DEVPKG bf957
DEVPKGTIME 1225368784
DEVSPEED -4
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE rev.vhdl
STIMULUS test2.tbw
SOURCE xmit.vhdl
[Normal]
xilxBitgStart_Clk=xstvhd, virtex2, VHDL.t_bitFile, 1225368861, JTAG Clock
[STRATEGY-LIST]
Normal=True