test5.vhw

xilinx环境下开发vhdl语言串行接口设计

-- E:\AA
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Fri Oct 31 15:31:06 2008
-- 
-- Notes:
-- 1) This testbench has been automatically generated from
--   your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
--   - Save it as a file with a .vhd extension (i.e. File->Save As...)
--   - Add it to your project as a testbench source (i.e. Project->Add Source...)
-- 

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY test5 IS
END test5;

ARCHITECTURE testbench_arch OF test5 IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
	COMPONENT ctrl
		PORT (
			rst : In  std_logic;
			npreq : In  std_logic;
			nprd : In  std_logic;
			npwr : In  std_logic;
			ioab : In  std_logic_vector (1 DOWNTO 0);
			iodb : InOut  std_logic_vector (7 DOWNTO 0);
			tdata : Out  std_logic_vector (7 DOWNTO 0);
			rdata : In  std_logic_vector (7 DOWNTO 0);
			rcving : In  std_logic;
			done_rcving : In  std_logic;
			xmitting : In  std_logic;
			done_xmitting : In  std_logic
		);
	END COMPONENT;

	SIGNAL rst : std_logic;
	SIGNAL npreq : std_logic;
	SIGNAL nprd : std_logic;
	SIGNAL npwr : std_logic;
	SIGNAL ioab : std_logic_vector (1 DOWNTO 0);
	SIGNAL iodb : std_logic_vector (7 DOWNTO 0);
	SIGNAL tdata : std_logic_vector (7 DOWNTO 0);
	SIGNAL rdata : std_logic_vector (7 DOWNTO 0);
	SIGNAL rcving : std_logic;
	SIGNAL done_rcving : std_logic;
	SIGNAL xmitting : std_logic;
	SIGNAL done_xmitting : std_logic;

BEGIN
	UUT : ctrl
	PORT MAP (
		rst => rst,
		npreq => npreq,
		nprd => nprd,
		npwr => npwr,
		ioab => ioab,
		iodb => iodb,
		tdata => tdata,
		rdata => rdata,
		rcving => rcving,
		done_rcving => done_rcving,
		xmitting => xmitting,
		done_xmitting => done_xmitting
	);

	PROCESS
		VARIABLE TX_OUT : LINE;
		VARIABLE TX_ERROR : INTEGER := 0;

		PROCEDURE CHECK_tdata(
			next_tdata : std_logic_vector (7 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (tdata /= next_tdata) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns tdata="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, tdata);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_tdata);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_iodb(
			next_iodb : std_logic_vector (7 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (iodb /= next_iodb) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns iodb="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, iodb);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_iodb);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		BEGIN
		-- --------------------
		rst <= transport '0';
		npreq <= transport '0';
		nprd <= transport '0';
		npwr <= transport '0';
		ioab <= transport std_logic_vector'("00"); --0
		rdata <= transport std_logic_vector'("00000000"); --0
		rcving <= transport '0';
		done_rcving <= transport '0';
		xmitting <= transport '0';
		done_xmitting <= transport '0';
		iodb <= transport std_logic_vector'("ZZZZZZZZ"); --Z
		-- --------------------
		WAIT FOR 100 ns; -- Time=100 ns
		rst <= transport '1';
		ioab <= transport std_logic_vector'("00"); --0
		rdata <= transport std_logic_vector'("01001010"); --4A
		done_xmitting <= transport '1';
		iodb <= transport std_logic_vector'("01001011"); --4B
		-- --------------------
		WAIT FOR 100 ns; -- Time=200 ns
		npreq <= transport '1';
		npwr <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=300 ns
		ioab <= transport std_logic_vector'("00"); --0
		-- --------------------
		WAIT FOR 100 ns; -- Time=400 ns
		ioab <= transport std_logic_vector'("00"); --0
		rdata <= transport std_logic_vector'("11010010"); --D2
		-- --------------------
		WAIT FOR 100 ns; -- Time=500 ns
		rst <= transport '0';
		npwr <= transport '0';
		ioab <= transport std_logic_vector'("00"); --0
		-- --------------------
		WAIT FOR 100 ns; -- Time=600 ns
		rst <= transport '1';
		nprd <= transport '1';
		ioab <= transport std_logic_vector'("01"); --1
		rcving <= transport '1';
		iodb <= transport std_logic_vector'("ZZZZZZZZ"); --Z
		-- --------------------
		WAIT FOR 50 ns; -- Time=650 ns
		CHECK_iodb("ZZZZZZZZ",650); --Z
		-- --------------------
		WAIT FOR 50 ns; -- Time=700 ns
		npwr <= transport '0';
		ioab <= transport std_logic_vector'("01"); --1
		rcving <= transport '0';
		xmitting <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=800 ns
		npwr <= transport '0';
		rcving <= transport '1';
		done_rcving <= transport '0';
		xmitting <= transport '0';
		-- --------------------
		WAIT FOR 200 ns; -- Time=1000 ns
		npreq <= transport '0';
		-- --------------------
		WAIT FOR 1900 ns; -- Time=2900 ns
		-- --------------------

		IF (TX_ERROR = 0) THEN 
			STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Simulation successful (not a failure).  No problems detected. "
				SEVERITY FAILURE;
		ELSE
			STD.TEXTIO.write(TX_OUT, TX_ERROR);
			STD.TEXTIO.write(TX_OUT, string'(
				" errors found in simulation"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Errors found during simulation"
				SEVERITY FAILURE;
		END IF;
	END PROCESS;
END testbench_arch;

CONFIGURATION ctrl_cfg OF test5 IS
	FOR testbench_arch
	END FOR;
END ctrl_cfg;