test2.ant

xilinx环境下开发vhdl语言串行接口设计

-- E:\AA
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Fri Oct 31 13:45:57 2008

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY test2 IS
END test2;

ARCHITECTURE testbench_arch OF test2 IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "e:\aa\test2.ano";
	COMPONENT rev
		PORT (
			clrn : In  std_logic;
			clktr : In  std_logic;
			rxd : In  std_logic;
			rdata : Out  std_logic_vector (7 DOWNTO 0);
			rcving : Out  std_logic;
			done_rcving : Out  std_logic;
			enclk : Out  std_logic
		);
	END COMPONENT;

	SIGNAL clrn : std_logic;
	SIGNAL clktr : std_logic;
	SIGNAL rxd : std_logic;
	SIGNAL rdata : std_logic_vector (7 DOWNTO 0);
	SIGNAL rcving : std_logic;
	SIGNAL done_rcving : std_logic;
	SIGNAL enclk : std_logic;

BEGIN
	UUT : rev
	PORT MAP (
		clrn => clrn,
		clktr => clktr,
		rxd => rxd,
		rdata => rdata,
		rcving => rcving,
		done_rcving => done_rcving,
		enclk => enclk
	);

	PROCESS -- clock process for clktr,
		VARIABLE TX_TIME : INTEGER :=0;

		PROCEDURE ANNOTATE_rdata(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",rdata,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, rdata);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_rcving(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",rcving,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, rcving);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_done_rcving(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",done_rcving,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, done_rcving);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_enclk(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",enclk,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, enclk);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CLOCK_LOOP : LOOP
		clktr <= transport '0';
		WAIT FOR 10 ns;
		TX_TIME := TX_TIME + 10;
		clktr <= transport '1';
		WAIT FOR 10 ns;
		TX_TIME := TX_TIME + 10;
		ANNOTATE_rdata(TX_TIME);
		ANNOTATE_rcving(TX_TIME);
		ANNOTATE_done_rcving(TX_TIME);
		ANNOTATE_enclk(TX_TIME);
		WAIT FOR 40 ns;
		TX_TIME := TX_TIME + 40;
		clktr <= transport '0';
		WAIT FOR 40 ns;
		TX_TIME := TX_TIME + 40;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clktr
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		rxd <= transport '1';
		clrn <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=100 ns
		clrn <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=200 ns
		rxd <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=300 ns
		rxd <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=400 ns
		rxd <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=500 ns
		rxd <= transport '0';
		-- --------------------
		WAIT FOR 200 ns; -- Time=700 ns
		rxd <= transport '1';
		-- --------------------
		WAIT FOR 200 ns; -- Time=900 ns
		rxd <= transport '0';
		-- --------------------
		WAIT FOR 500 ns; -- Time=1400 ns
		rxd <= transport '1';
		-- --------------------
		WAIT FOR 860 ns; -- Time=2260 ns
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION rev_cfg OF test2 IS
	FOR testbench_arch
	END FOR;
END rev_cfg;