xmit.syr

xilinx环境下开发vhdl语言串行接口设计

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clrn                               | IBUF                   | 1     |
_n0046(_n0046_SW129:O)             | NONE(*)(done_xmitting) | 1     |
_n0045(_n0045:O)                   | NONE(*)(xmitting)      | 1     |
clktr                              | IBUF                   | 4     |
-----------------------------------+------------------------+-------+
(*) These 2 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 3.164ns (Maximum Frequency: 316.056MHz)
   Minimum input arrival time before clock: 4.603ns
   Maximum output required time after clock: 5.760ns
   Maximum combinational path delay: 6.003ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clrn'
Delay:               3.164ns (Levels of Logic = 2)
  Source:            txd (LATCH)
  Destination:       txd (LATCH)
  Source Clock:      clrn falling
  Destination Clock: clrn falling

  Data Path: txd to txd
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               3   0.674   0.725  txd (txd_OBUF)
     LUT4:I2->O            1   0.439   0.517  _n000543 (CHOICE215)
     LUT4_L:I0->LO         1   0.439   0.000  _n0005179 (_n0005)
     LD:D                      0.370          txd
    ----------------------------------------
    Total                      3.164ns (1.922ns logic, 1.242ns route)
                                       (60.7% logic, 39.3% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clktr'
Delay:               2.355ns (Levels of Logic = 1)
  Source:            count_1 (FF)
  Destination:       count_0 (FF)
  Source Clock:      clktr rising
  Destination Clock: clktr rising

  Data Path: count_1 to count_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             14   0.568   0.977  count_1 (count_1)
     LUT2_L:I1->LO         1   0.439   0.000  count_Mmux__n0001_Result<1>1 (count__n0001<1>)
     FDC:D                     0.370          count_1
    ----------------------------------------
    Total                      2.355ns (1.377ns logic, 0.977ns route)
                                       (58.5% logic, 41.5% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clrn'
Offset:              4.603ns (Levels of Logic = 5)
  Source:            tdata<5> (PAD)
  Destination:       txd (LATCH)
  Destination Clock: clrn falling

  Data Path: tdata<5> to txd
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.825   0.517  tdata_5_IBUF (tdata_5_IBUF)
     LUT4:I2->O            1   0.439   0.517  _n0005103 (CHOICE226)
     LUT4:I1->O            1   0.439   0.517  _n0005147 (CHOICE235)
     LUT3_L:I2->LO         1   0.439   0.100  _n0005166 (CHOICE239)
     LUT4_L:I1->LO         1   0.439   0.000  _n0005179 (_n0005)
     LD:D                      0.370          txd
    ----------------------------------------
    Total                      4.603ns (2.951ns logic, 1.652ns route)
                                       (64.1% logic, 35.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock '_n0046_SW129:O'
Offset:              3.407ns (Levels of Logic = 3)
  Source:            clrn (PAD)
  Destination:       done_xmitting (LATCH)
  Destination Clock: _n0046_SW129:O falling

  Data Path: clrn to done_xmitting
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             7   0.825   0.816  clrn_IBUF (enclk_OBUF)
     LUT2:I1->O            1   0.439   0.517  _n0009_SW0 (N1899)
     LUT4:I0->O            1   0.439   0.000  _n0009 (_n0009)
     LD:D                      0.370          done_xmitting
    ----------------------------------------
    Total                      3.407ns (2.073ns logic, 1.334ns route)
                                       (60.8% logic, 39.2% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock '_n0045:O'
Offset:              3.407ns (Levels of Logic = 3)
  Source:            clrn (PAD)
  Destination:       xmitting (LATCH)
  Destination Clock: _n0045:O falling

  Data Path: clrn to xmitting
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             7   0.825   0.816  clrn_IBUF (enclk_OBUF)
     LUT2:I1->O            1   0.439   0.517  _n0007_SW0 (N1925)
     LUT4:I3->O            1   0.439   0.000  _n0007 (_n0007)
     LD:D                      0.370          xmitting
    ----------------------------------------
    Total                      3.407ns (2.073ns logic, 1.334ns route)
                                       (60.8% logic, 39.2% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock '_n0046_SW129:O'
Offset:              5.552ns (Levels of Logic = 1)
  Source:            done_xmitting (LATCH)
  Destination:       done_xmitting (PAD)
  Source Clock:      _n0046_SW129:O falling

  Data Path: done_xmitting to done_xmitting
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   0.674   0.517  done_xmitting (done_xmitting_OBUF)
     OBUF:I->O                 4.361          done_xmitting_OBUF (done_xmitting)
    ----------------------------------------
    Total                      5.552ns (5.035ns logic, 0.517ns route)
                                       (90.7% logic, 9.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clrn'
Offset:              5.760ns (Levels of Logic = 1)
  Source:            txd (LATCH)
  Destination:       txd (PAD)
  Source Clock:      clrn falling

  Data Path: txd to txd
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               3   0.674   0.725  txd (txd_OBUF)
     OBUF:I->O                 4.361          txd_OBUF (txd)
    ----------------------------------------
    Total                      5.760ns (5.035ns logic, 0.725ns route)
                                       (87.4% logic, 12.6% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock '_n0045:O'
Offset:              5.552ns (Levels of Logic = 1)
  Source:            xmitting (LATCH)
  Destination:       xmitting (PAD)
  Source Clock:      _n0045:O falling

  Data Path: xmitting to xmitting
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   0.674   0.517  xmitting (xmitting_OBUF)
     OBUF:I->O                 4.361          xmitting_OBUF (xmitting)
    ----------------------------------------
    Total                      5.552ns (5.035ns logic, 0.517ns route)
                                       (90.7% logic, 9.3% route)

-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               6.003ns (Levels of Logic = 2)
  Source:            clrn (PAD)
  Destination:       enclk (PAD)

  Data Path: clrn to enclk
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             7   0.825   0.816  clrn_IBUF (enclk_OBUF)
     OBUF:I->O                 4.361          enclk_OBUF (enclk)
    ----------------------------------------
    Total                      6.003ns (5.186ns logic, 0.816ns route)
                                       (86.4% logic, 13.6% route)

=========================================================================
CPU : 2.55 / 3.13 s | Elapsed : 2.00 / 3.00 s
 
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Total memory usage is 90832 kilobytes