xmit.syr

xilinx环境下开发vhdl语言串行接口设计

Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.28 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
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--> Reading design: xmit.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : xmit.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : xmit
Output Format                      : NGC
Target Device                      : xc2v2000-4-bf957

---- Source Options
Top Module Name                    : xmit
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 0
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : xmit.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/WorkSpace/Xilinx/dl/aa/xmit.vhdl in Library work.
Entity <xmit> (Architecture <main>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <xmit> (Architecture <main>).
WARNING:Xst:819 - D:/WorkSpace/Xilinx/dl/aa/xmit.vhdl line 45: The following signals are missing in the process sensitivity list:
   tdata.
Entity <xmit> analyzed. Unit <xmit> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <xmit>.
    Related source file is D:/WorkSpace/Xilinx/dl/aa/xmit.vhdl.
WARNING:Xst:737 - Found 1-bit latch for signal <txd>.
WARNING:Xst:737 - Found 1-bit latch for signal <xmitting>.
WARNING:Xst:737 - Found 1-bit latch for signal <done_xmitting>.
    Found 4-bit up counter for signal <count>.
    Summary:
	inferred   1 Counter(s).
Unit <xmit> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 4-bit up counter                  : 1
# Latches                          : 3
 1-bit latch                       : 3

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <xmit> ...
Loading device for application Xst from file '2v2000.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block xmit, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : xmit.ngr
Top Level Output File Name         : xmit
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 14

Macro Statistics :
# Registers                        : 1
#      4-bit register              : 1
# Multiplexers                     : 1
#      2-to-1 multiplexer          : 1

Cell Usage :
# BELS                             : 24
#      LUT1                        : 1
#      LUT2                        : 3
#      LUT2_L                      : 1
#      LUT3                        : 5
#      LUT3_L                      : 1
#      LUT4                        : 9
#      LUT4_L                      : 4
# FlipFlops/Latches                : 7
#      FDC                         : 4
#      LD                          : 3
# IO Buffers                       : 14
#      IBUF                        : 10
#      OBUF                        : 4
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2v2000bf957-4 

 Number of Slices:                      14  out of  10752     0%  
 Number of Slice Flip Flops:             7  out of  21504     0%  
 Number of 4 input LUTs:                24  out of  21504     0%  
 Number of bonded IOBs:                 14  out of    624     2%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.