rev.syr

xilinx环境下开发vhdl语言串行接口设计

    ----------------------------------------
    Total                      2.057ns (1.195ns logic, 0.862ns route)
                                       (58.1% logic, 41.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock '_n00141:O'
Offset:              2.057ns (Levels of Logic = 1)
  Source:            rxd (PAD)
  Destination:       rdata_5 (LATCH)
  Destination Clock: _n00141:O falling

  Data Path: rxd to rdata_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             9   0.825   0.862  rxd_IBUF (rxd_IBUF)
     LDC:D                     0.370          rdata_5
    ----------------------------------------
    Total                      2.057ns (1.195ns logic, 0.862ns route)
                                       (58.1% logic, 41.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock '_n00191:O'
Offset:              2.057ns (Levels of Logic = 1)
  Source:            rxd (PAD)
  Destination:       rdata_0 (LATCH)
  Destination Clock: _n00191:O falling

  Data Path: rxd to rdata_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             9   0.825   0.862  rxd_IBUF (rxd_IBUF)
     LDC:D                     0.370          rdata_0
    ----------------------------------------
    Total                      2.057ns (1.195ns logic, 0.862ns route)
                                       (58.1% logic, 41.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock '_n00181:O'
Offset:              2.057ns (Levels of Logic = 1)
  Source:            rxd (PAD)
  Destination:       rdata_1 (LATCH)
  Destination Clock: _n00181:O falling

  Data Path: rxd to rdata_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             9   0.825   0.862  rxd_IBUF (rxd_IBUF)
     LDC:D                     0.370          rdata_1
    ----------------------------------------
    Total                      2.057ns (1.195ns logic, 0.862ns route)
                                       (58.1% logic, 41.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock '_n00171:O'
Offset:              2.057ns (Levels of Logic = 1)
  Source:            rxd (PAD)
  Destination:       rdata_2 (LATCH)
  Destination Clock: _n00171:O falling

  Data Path: rxd to rdata_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             9   0.825   0.862  rxd_IBUF (rxd_IBUF)
     LDC:D                     0.370          rdata_2
    ----------------------------------------
    Total                      2.057ns (1.195ns logic, 0.862ns route)
                                       (58.1% logic, 41.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock '_n00161:O'
Offset:              2.057ns (Levels of Logic = 1)
  Source:            rxd (PAD)
  Destination:       rdata_3 (LATCH)
  Destination Clock: _n00161:O falling

  Data Path: rxd to rdata_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             9   0.825   0.862  rxd_IBUF (rxd_IBUF)
     LDC:D                     0.370          rdata_3
    ----------------------------------------
    Total                      2.057ns (1.195ns logic, 0.862ns route)
                                       (58.1% logic, 41.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock '_n00131:O'
Offset:              2.057ns (Levels of Logic = 1)
  Source:            rxd (PAD)
  Destination:       rdata_6 (LATCH)
  Destination Clock: _n00131:O falling

  Data Path: rxd to rdata_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             9   0.825   0.862  rxd_IBUF (rxd_IBUF)
     LDC:D                     0.370          rdata_6
    ----------------------------------------
    Total                      2.057ns (1.195ns logic, 0.862ns route)
                                       (58.1% logic, 41.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock '_n00151:O'
Offset:              2.057ns (Levels of Logic = 1)
  Source:            rxd (PAD)
  Destination:       rdata_4 (LATCH)
  Destination Clock: _n00151:O falling

  Data Path: rxd to rdata_4
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             9   0.825   0.862  rxd_IBUF (rxd_IBUF)
     LDC:D                     0.370          rdata_4
    ----------------------------------------
    Total                      2.057ns (1.195ns logic, 0.862ns route)
                                       (58.1% logic, 41.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'startm1:O'
Offset:              5.446ns (Levels of Logic = 1)
  Source:            enclk (FF)
  Destination:       enclk (PAD)
  Source Clock:      startm1:O rising

  Data Path: enclk to enclk
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              1   0.568   0.517  enclk (enclk_OBUF)
     OBUF:I->O                 4.361          enclk_OBUF (enclk)
    ----------------------------------------
    Total                      5.446ns (4.929ns logic, 0.517ns route)
                                       (90.5% logic, 9.5% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock '_n00561:O'
Offset:              5.552ns (Levels of Logic = 1)
  Source:            done_rcving (LATCH)
  Destination:       done_rcving (PAD)
  Source Clock:      _n00561:O falling

  Data Path: done_rcving to done_rcving
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   0.674   0.517  done_rcving (done_rcving_OBUF)
     OBUF:I->O                 4.361          done_rcving_OBUF (done_rcving)
    ----------------------------------------
    Total                      5.552ns (5.035ns logic, 0.517ns route)
                                       (90.7% logic, 9.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock '_n00551:O'
Offset:              5.552ns (Levels of Logic = 1)
  Source:            rcving (LATCH)
  Destination:       rcving (PAD)
  Source Clock:      _n00551:O falling

  Data Path: rcving to rcving
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   0.674   0.517  rcving (rcving_OBUF)
     OBUF:I->O                 4.361          rcving_OBUF (rcving)
    ----------------------------------------
    Total                      5.552ns (5.035ns logic, 0.517ns route)
                                       (90.7% logic, 9.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock '_n00121:O'
Offset:              5.552ns (Levels of Logic = 1)
  Source:            rdata_7 (LATCH)
  Destination:       rdata<7> (PAD)
  Source Clock:      _n00121:O falling

  Data Path: rdata_7 to rdata<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDC:G->Q              1   0.674   0.517  rdata_7 (rdata_7)
     OBUF:I->O                 4.361          rdata_7_OBUF (rdata<7>)
    ----------------------------------------
    Total                      5.552ns (5.035ns logic, 0.517ns route)
                                       (90.7% logic, 9.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock '_n00131:O'
Offset:              5.552ns (Levels of Logic = 1)
  Source:            rdata_6 (LATCH)
  Destination:       rdata<6> (PAD)
  Source Clock:      _n00131:O falling

  Data Path: rdata_6 to rdata<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDC:G->Q              1   0.674   0.517  rdata_6 (rdata_6)
     OBUF:I->O                 4.361          rdata_6_OBUF (rdata<6>)
    ----------------------------------------
    Total                      5.552ns (5.035ns logic, 0.517ns route)
                                       (90.7% logic, 9.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock '_n00141:O'
Offset:              5.552ns (Levels of Logic = 1)
  Source:            rdata_5 (LATCH)
  Destination:       rdata<5> (PAD)
  Source Clock:      _n00141:O falling

  Data Path: rdata_5 to rdata<5>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDC:G->Q              1   0.674   0.517  rdata_5 (rdata_5)
     OBUF:I->O                 4.361          rdata_5_OBUF (rdata<5>)
    ----------------------------------------
    Total                      5.552ns (5.035ns logic, 0.517ns route)
                                       (90.7% logic, 9.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock '_n00151:O'
Offset:              5.552ns (Levels of Logic = 1)
  Source:            rdata_4 (LATCH)
  Destination:       rdata<4> (PAD)
  Source Clock:      _n00151:O falling

  Data Path: rdata_4 to rdata<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDC:G->Q              1   0.674   0.517  rdata_4 (rdata_4)
     OBUF:I->O                 4.361          rdata_4_OBUF (rdata<4>)
    ----------------------------------------
    Total                      5.552ns (5.035ns logic, 0.517ns route)
                                       (90.7% logic, 9.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock '_n00161:O'
Offset:              5.552ns (Levels of Logic = 1)
  Source:            rdata_3 (LATCH)
  Destination:       rdata<3> (PAD)
  Source Clock:      _n00161:O falling

  Data Path: rdata_3 to rdata<3>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDC:G->Q              1   0.674   0.517  rdata_3 (rdata_3)
     OBUF:I->O                 4.361          rdata_3_OBUF (rdata<3>)
    ----------------------------------------
    Total                      5.552ns (5.035ns logic, 0.517ns route)
                                       (90.7% logic, 9.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock '_n00171:O'
Offset:              5.552ns (Levels of Logic = 1)
  Source:            rdata_2 (LATCH)
  Destination:       rdata<2> (PAD)
  Source Clock:      _n00171:O falling

  Data Path: rdata_2 to rdata<2>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDC:G->Q              1   0.674   0.517  rdata_2 (rdata_2)
     OBUF:I->O                 4.361          rdata_2_OBUF (rdata<2>)
    ----------------------------------------
    Total                      5.552ns (5.035ns logic, 0.517ns route)
                                       (90.7% logic, 9.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock '_n00181:O'
Offset:              5.552ns (Levels of Logic = 1)
  Source:            rdata_1 (LATCH)
  Destination:       rdata<1> (PAD)
  Source Clock:      _n00181:O falling

  Data Path: rdata_1 to rdata<1>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDC:G->Q              1   0.674   0.517  rdata_1 (rdata_1)
     OBUF:I->O                 4.361          rdata_1_OBUF (rdata<1>)
    ----------------------------------------
    Total                      5.552ns (5.035ns logic, 0.517ns route)
                                       (90.7% logic, 9.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock '_n00191:O'
Offset:              5.552ns (Levels of Logic = 1)
  Source:            rdata_0 (LATCH)
  Destination:       rdata<0> (PAD)
  Source Clock:      _n00191:O falling

  Data Path: rdata_0 to rdata<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDC:G->Q              1   0.674   0.517  rdata_0 (rdata_0)
     OBUF:I->O                 4.361          rdata_0_OBUF (rdata<0>)
    ----------------------------------------
    Total                      5.552ns (5.035ns logic, 0.517ns route)
                                       (90.7% logic, 9.3% route)

=========================================================================
CPU : 2.44 / 3.02 s | Elapsed : 3.00 / 3.00 s
 
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Total memory usage is 90832 kilobytes