rev.syr

xilinx环境下开发vhdl语言串行接口设计

Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: rev.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : rev.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : rev
Output Format                      : NGC
Target Device                      : xc2v2000-4-bf957

---- Source Options
Top Module Name                    : rev
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 0
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : rev.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/WorkSpace/Xilinx/dl/aa/rev.vhdl in Library work.
Entity <rev> (Architecture <main>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <rev> (Architecture <main>).
WARNING:Xst:819 - D:/WorkSpace/Xilinx/dl/aa/rev.vhdl line 58: The following signals are missing in the process sensitivity list:
   rxd.
Entity <rev> analyzed. Unit <rev> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <rev>.
    Related source file is D:/WorkSpace/Xilinx/dl/aa/rev.vhdl.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_7>.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_6>.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_5>.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_4>.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_3>.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_2>.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_1>.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_0>.
WARNING:Xst:737 - Found 1-bit latch for signal <rcving>.
WARNING:Xst:737 - Found 1-bit latch for signal <done_rcving>.
    Found 1-bit register for signal <enclk>.
    Found 4-bit up counter for signal <count>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <rev> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 4-bit up counter                  : 1
# Registers                        : 1
 1-bit register                    : 1
# Latches                          : 10
 1-bit latch                       : 10

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <rev> ...
Loading device for application Xst from file '2v2000.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block rev, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : rev.ngr
Top Level Output File Name         : rev
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 14

Macro Statistics :
# Registers                        : 2
#      1-bit register              : 1
#      4-bit register              : 1
# Multiplexers                     : 1
#      2-to-1 multiplexer          : 1

Cell Usage :
# BELS                             : 20
#      LUT1                        : 1
#      LUT2                        : 2
#      LUT3_L                      : 1
#      LUT4                        : 12
#      LUT4_L                      : 3
#      VCC                         : 1
# FlipFlops/Latches                : 15
#      FDC                         : 1
#      FDC_1                       : 4
#      LD                          : 2
#      LDC                         : 8
# IO Buffers                       : 14
#      IBUF                        : 3
#      OBUF                        : 11
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2v2000bf957-4 

 Number of Slices:                      12  out of  10752     0%  
 Number of Slice Flip Flops:            15  out of  21504     0%  
 Number of 4 input LUTs:                19  out of  21504     0%  
 Number of bonded IOBs:                 14  out of    624     2%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
_n0056(_n00561:O)                  | NONE(*)(done_rcving)   | 1     |
_n0055(_n00551:O)                  | NONE(*)(rcving)        | 1     |
_n0012(_n00121:O)                  | NONE(*)(rdata_7)       | 1     |
_n0014(_n00141:O)                  | NONE(*)(rdata_5)       | 1     |
_n0019(_n00191:O)                  | NONE(*)(rdata_0)       | 1     |
clktr                              | IBUF                   | 4     |
_n0018(_n00181:O)                  | NONE(*)(rdata_1)       | 1     |
_n0017(_n00171:O)                  | NONE(*)(rdata_2)       | 1     |
_n0016(_n00161:O)                  | NONE(*)(rdata_3)       | 1     |
_n0013(_n00131:O)                  | NONE(*)(rdata_6)       | 1     |
_n0015(_n00151:O)                  | NONE(*)(rdata_4)       | 1     |
startm(startm1:O)                  | NONE(*)(enclk)         | 1     |
-----------------------------------+------------------------+-------+
(*) These 11 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 2.378ns (Maximum Frequency: 420.610MHz)
   Minimum input arrival time before clock: 2.427ns
   Maximum output required time after clock: 5.552ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clktr'
Delay:               2.378ns (Levels of Logic = 1)
  Source:            count_0 (FF)
  Destination:       count_3 (FF)
  Source Clock:      clktr falling
  Destination Clock: clktr falling

  Data Path: count_0 to count_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q           16   0.568   1.000  count_0 (count_0)
     LUT4_L:I1->LO         1   0.439   0.000  count_Mmux__n0001_Result<3>1 (count__n0001<3>)
     FDC_1:D                   0.370          count_3
    ----------------------------------------
    Total                      2.378ns (1.377ns logic, 1.000ns route)
                                       (57.9% logic, 42.1% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock '_n00561:O'
Offset:              2.427ns (Levels of Logic = 2)
  Source:            clrn (PAD)
  Destination:       done_rcving (LATCH)
  Destination Clock: _n00561:O falling

  Data Path: clrn to done_rcving
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             6   0.825   0.793  clrn_IBUF (clrn_IBUF)
     LUT4:I2->O            1   0.439   0.000  _n00301 (_n0030)
     LD:D                      0.370          done_rcving
    ----------------------------------------
    Total                      2.427ns (1.634ns logic, 0.793ns route)
                                       (67.3% logic, 32.7% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock '_n00551:O'
Offset:              2.427ns (Levels of Logic = 2)
  Source:            clrn (PAD)
  Destination:       rcving (LATCH)
  Destination Clock: _n00551:O falling

  Data Path: clrn to rcving
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             6   0.825   0.793  clrn_IBUF (clrn_IBUF)
     LUT4:I1->O            1   0.439   0.000  _n00211 (_n0021)
     LD:D                      0.370          rcving
    ----------------------------------------
    Total                      2.427ns (1.634ns logic, 0.793ns route)
                                       (67.3% logic, 32.7% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock '_n00121:O'
Offset:              2.057ns (Levels of Logic = 1)
  Source:            rxd (PAD)
  Destination:       rdata_7 (LATCH)
  Destination Clock: _n00121:O falling

  Data Path: rxd to rdata_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             9   0.825   0.862  rxd_IBUF (rxd_IBUF)
     LDC:D                     0.370          rdata_7