rs232_rec5.tan.qmsg

VHDL语言实现的穿行通讯

{ "Info" "ITDB_TH_RESULT" "rs232_rec2:inst1\|rxd_reg1 pin_rxd pin_clk -1.575 ns register " "Info: th for register \"rs232_rec2:inst1\|rxd_reg1\" (data pin = \"pin_rxd\", clock pin = \"pin_clk\") is -1.575 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pin_clk destination 6.437 ns + Longest register " "Info: + Longest clock path from clock \"pin_clk\" to destination register is 6.437 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns pin_clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'pin_clk'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_clk } "NODE_NAME" } } { "rs232_rec5.bdf" "" { Schematic "D:/fpga_dev/rs232_rec5/rs232_rec5.bdf" { { 104 16 184 120 "pin_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.347 ns) + CELL(0.970 ns) 3.457 ns rs232_rec2:inst1\|clkbaud8x 2 REG LCFF_X6_Y6_N17 3 " "Info: 2: + IC(1.347 ns) + CELL(0.970 ns) = 3.457 ns; Loc. = LCFF_X6_Y6_N17; Fanout = 3; REG Node = 'rs232_rec2:inst1\|clkbaud8x'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.317 ns" { pin_clk rs232_rec2:inst1|clkbaud8x } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.479 ns) + CELL(0.000 ns) 4.936 ns rs232_rec2:inst1\|clkbaud8x~clkctrl 3 COMB CLKCTRL_G1 54 " "Info: 3: + IC(1.479 ns) + CELL(0.000 ns) = 4.936 ns; Loc. = CLKCTRL_G1; Fanout = 54; COMB Node = 'rs232_rec2:inst1\|clkbaud8x~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.479 ns" { rs232_rec2:inst1|clkbaud8x rs232_rec2:inst1|clkbaud8x~clkctrl } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.835 ns) + CELL(0.666 ns) 6.437 ns rs232_rec2:inst1\|rxd_reg1 4 REG LCFF_X22_Y5_N19 2 " "Info: 4: + IC(0.835 ns) + CELL(0.666 ns) = 6.437 ns; Loc. = LCFF_X22_Y5_N19; Fanout = 2; REG Node = 'rs232_rec2:inst1\|rxd_reg1'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.501 ns" { rs232_rec2:inst1|clkbaud8x~clkctrl rs232_rec2:inst1|rxd_reg1 } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 43.13 % ) " "Info: Total cell delay = 2.776 ns ( 43.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.661 ns ( 56.87 % ) " "Info: Total interconnect delay = 3.661 ns ( 56.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.437 ns" { pin_clk rs232_rec2:inst1|clkbaud8x rs232_rec2:inst1|clkbaud8x~clkctrl rs232_rec2:inst1|rxd_reg1 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.437 ns" { pin_clk {} pin_clk~combout {} rs232_rec2:inst1|clkbaud8x {} rs232_rec2:inst1|clkbaud8x~clkctrl {} rs232_rec2:inst1|rxd_reg1 {} } { 0.000ns 0.000ns 1.347ns 1.479ns 0.835ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 47 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.318 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.318 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.005 ns) 1.005 ns pin_rxd 1 PIN PIN_145 5 " "Info: 1: + IC(0.000 ns) + CELL(1.005 ns) = 1.005 ns; Loc. = PIN_145; Fanout = 5; PIN Node = 'pin_rxd'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_rxd } "NODE_NAME" } } { "rs232_rec5.bdf" "" { Schematic "D:/fpga_dev/rs232_rec5/rs232_rec5.bdf" { { 136 16 184 152 "pin_rxd" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.999 ns) + CELL(0.206 ns) 8.210 ns rs232_rec2:inst1\|rxd_reg1~feeder 2 COMB LCCOMB_X22_Y5_N18 1 " "Info: 2: + IC(6.999 ns) + CELL(0.206 ns) = 8.210 ns; Loc. = LCCOMB_X22_Y5_N18; Fanout = 1; COMB Node = 'rs232_rec2:inst1\|rxd_reg1~feeder'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.205 ns" { pin_rxd rs232_rec2:inst1|rxd_reg1~feeder } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 8.318 ns rs232_rec2:inst1\|rxd_reg1 3 REG LCFF_X22_Y5_N19 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 8.318 ns; Loc. = LCFF_X22_Y5_N19; Fanout = 2; REG Node = 'rs232_rec2:inst1\|rxd_reg1'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { rs232_rec2:inst1|rxd_reg1~feeder rs232_rec2:inst1|rxd_reg1 } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.319 ns ( 15.86 % ) " "Info: Total cell delay = 1.319 ns ( 15.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.999 ns ( 84.14 % ) " "Info: Total interconnect delay = 6.999 ns ( 84.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.318 ns" { pin_rxd rs232_rec2:inst1|rxd_reg1~feeder rs232_rec2:inst1|rxd_reg1 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.318 ns" { pin_rxd {} pin_rxd~combout {} rs232_rec2:inst1|rxd_reg1~feeder {} rs232_rec2:inst1|rxd_reg1 {} } { 0.000ns 0.000ns 6.999ns 0.000ns } { 0.000ns 1.005ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.437 ns" { pin_clk rs232_rec2:inst1|clkbaud8x rs232_rec2:inst1|clkbaud8x~clkctrl rs232_rec2:inst1|rxd_reg1 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.437 ns" { pin_clk {} pin_clk~combout {} rs232_rec2:inst1|clkbaud8x {} rs232_rec2:inst1|clkbaud8x~clkctrl {} rs232_rec2:inst1|rxd_reg1 {} } { 0.000ns 0.000ns 1.347ns 1.479ns 0.835ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.318 ns" { pin_rxd rs232_rec2:inst1|rxd_reg1~feeder rs232_rec2:inst1|rxd_reg1 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.318 ns" { pin_rxd {} pin_rxd~combout {} rs232_rec2:inst1|rxd_reg1~feeder {} rs232_rec2:inst1|rxd_reg1 {} } { 0.000ns 0.000ns 6.999ns 0.000ns } { 0.000ns 1.005ns 0.206ns 0.108ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "114 " "Info: Allocated 114 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 31 15:42:27 2008 " "Info: Processing ended: Mon Mar 31 15:42:27 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}