rs232_rec5.tan.qmsg

VHDL语言实现的穿行通讯

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "rs232_rec2:inst1\|clkbaud8x " "Info: Detected ripple clock \"rs232_rec2:inst1\|clkbaud8x\" as buffer" {  } { { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 42 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "rs232_rec2:inst1\|clkbaud8x" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "pin_clk register rs232_rec2:inst1\|state_rec\[2\] register rs232_rec2:inst1\|rxd_buf\[0\] 206.02 MHz 4.854 ns Internal " "Info: Clock \"pin_clk\" has Internal fmax of 206.02 MHz between source register \"rs232_rec2:inst1\|state_rec\[2\]\" and destination register \"rs232_rec2:inst1\|rxd_buf\[0\]\" (period= 4.854 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.586 ns + Longest register register " "Info: + Longest register to register delay is 4.586 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rs232_rec2:inst1\|state_rec\[2\] 1 REG LCFF_X21_Y5_N7 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y5_N7; Fanout = 5; REG Node = 'rs232_rec2:inst1\|state_rec\[2\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rs232_rec2:inst1|state_rec[2] } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 211 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.147 ns) + CELL(0.534 ns) 1.681 ns rs232_rec2:inst1\|Equal3~42 2 COMB LCCOMB_X22_Y5_N26 12 " "Info: 2: + IC(1.147 ns) + CELL(0.534 ns) = 1.681 ns; Loc. = LCCOMB_X22_Y5_N26; Fanout = 12; COMB Node = 'rs232_rec2:inst1\|Equal3~42'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.681 ns" { rs232_rec2:inst1|state_rec[2] rs232_rec2:inst1|Equal3~42 } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.708 ns) + CELL(0.370 ns) 2.759 ns rs232_rec2:inst1\|rxd_buf\[7\]~634 3 COMB LCCOMB_X21_Y5_N12 8 " "Info: 3: + IC(0.708 ns) + CELL(0.370 ns) = 2.759 ns; Loc. = LCCOMB_X21_Y5_N12; Fanout = 8; COMB Node = 'rs232_rec2:inst1\|rxd_buf\[7\]~634'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.078 ns" { rs232_rec2:inst1|Equal3~42 rs232_rec2:inst1|rxd_buf[7]~634 } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 211 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.972 ns) + CELL(0.855 ns) 4.586 ns rs232_rec2:inst1\|rxd_buf\[0\] 4 REG LCFF_X19_Y5_N19 1 " "Info: 4: + IC(0.972 ns) + CELL(0.855 ns) = 4.586 ns; Loc. = LCFF_X19_Y5_N19; Fanout = 1; REG Node = 'rs232_rec2:inst1\|rxd_buf\[0\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.827 ns" { rs232_rec2:inst1|rxd_buf[7]~634 rs232_rec2:inst1|rxd_buf[0] } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 211 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.759 ns ( 38.36 % ) " "Info: Total cell delay = 1.759 ns ( 38.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.827 ns ( 61.64 % ) " "Info: Total interconnect delay = 2.827 ns ( 61.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.586 ns" { rs232_rec2:inst1|state_rec[2] rs232_rec2:inst1|Equal3~42 rs232_rec2:inst1|rxd_buf[7]~634 rs232_rec2:inst1|rxd_buf[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.586 ns" { rs232_rec2:inst1|state_rec[2] {} rs232_rec2:inst1|Equal3~42 {} rs232_rec2:inst1|rxd_buf[7]~634 {} rs232_rec2:inst1|rxd_buf[0] {} } { 0.000ns 1.147ns 0.708ns 0.972ns } { 0.000ns 0.534ns 0.370ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.004 ns - Smallest " "Info: - Smallest clock skew is -0.004 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pin_clk destination 6.432 ns + Shortest register " "Info: + Shortest clock path from clock \"pin_clk\" to destination register is 6.432 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns pin_clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'pin_clk'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_clk } "NODE_NAME" } } { "rs232_rec5.bdf" "" { Schematic "D:/fpga_dev/rs232_rec5/rs232_rec5.bdf" { { 104 16 184 120 "pin_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.347 ns) + CELL(0.970 ns) 3.457 ns rs232_rec2:inst1\|clkbaud8x 2 REG LCFF_X6_Y6_N17 3 " "Info: 2: + IC(1.347 ns) + CELL(0.970 ns) = 3.457 ns; Loc. = LCFF_X6_Y6_N17; Fanout = 3; REG Node = 'rs232_rec2:inst1\|clkbaud8x'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.317 ns" { pin_clk rs232_rec2:inst1|clkbaud8x } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.479 ns) + CELL(0.000 ns) 4.936 ns rs232_rec2:inst1\|clkbaud8x~clkctrl 3 COMB CLKCTRL_G1 54 " "Info: 3: + IC(1.479 ns) + CELL(0.000 ns) = 4.936 ns; Loc. = CLKCTRL_G1; Fanout = 54; COMB Node = 'rs232_rec2:inst1\|clkbaud8x~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.479 ns" { rs232_rec2:inst1|clkbaud8x rs232_rec2:inst1|clkbaud8x~clkctrl } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.830 ns) + CELL(0.666 ns) 6.432 ns rs232_rec2:inst1\|rxd_buf\[0\] 4 REG LCFF_X19_Y5_N19 1 " "Info: 4: + IC(0.830 ns) + CELL(0.666 ns) = 6.432 ns; Loc. = LCFF_X19_Y5_N19; Fanout = 1; REG Node = 'rs232_rec2:inst1\|rxd_buf\[0\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.496 ns" { rs232_rec2:inst1|clkbaud8x~clkctrl rs232_rec2:inst1|rxd_buf[0] } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 211 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 43.16 % ) " "Info: Total cell delay = 2.776 ns ( 43.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.656 ns ( 56.84 % ) " "Info: Total interconnect delay = 3.656 ns ( 56.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.432 ns" { pin_clk rs232_rec2:inst1|clkbaud8x rs232_rec2:inst1|clkbaud8x~clkctrl rs232_rec2:inst1|rxd_buf[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.432 ns" { pin_clk {} pin_clk~combout {} rs232_rec2:inst1|clkbaud8x {} rs232_rec2:inst1|clkbaud8x~clkctrl {} rs232_rec2:inst1|rxd_buf[0] {} } { 0.000ns 0.000ns 1.347ns 1.479ns 0.830ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pin_clk source 6.436 ns - Longest register " "Info: - Longest clock path from clock \"pin_clk\" to source register is 6.436 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns pin_clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'pin_clk'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_clk } "NODE_NAME" } } { "rs232_rec5.bdf" "" { Schematic "D:/fpga_dev/rs232_rec5/rs232_rec5.bdf" { { 104 16 184 120 "pin_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.347 ns) + CELL(0.970 ns) 3.457 ns rs232_rec2:inst1\|clkbaud8x 2 REG LCFF_X6_Y6_N17 3 " "Info: 2: + IC(1.347 ns) + CELL(0.970 ns) = 3.457 ns; Loc. = LCFF_X6_Y6_N17; Fanout = 3; REG Node = 'rs232_rec2:inst1\|clkbaud8x'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.317 ns" { pin_clk rs232_rec2:inst1|clkbaud8x } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.479 ns) + CELL(0.000 ns) 4.936 ns rs232_rec2:inst1\|clkbaud8x~clkctrl 3 COMB CLKCTRL_G1 54 " "Info: 3: + IC(1.479 ns) + CELL(0.000 ns) = 4.936 ns; Loc. = CLKCTRL_G1; Fanout = 54; COMB Node = 'rs232_rec2:inst1\|clkbaud8x~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.479 ns" { rs232_rec2:inst1|clkbaud8x rs232_rec2:inst1|clkbaud8x~clkctrl } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.834 ns) + CELL(0.666 ns) 6.436 ns rs232_rec2:inst1\|state_rec\[2\] 4 REG LCFF_X21_Y5_N7 5 " "Info: 4: + IC(0.834 ns) + CELL(0.666 ns) = 6.436 ns; Loc. = LCFF_X21_Y5_N7; Fanout = 5; REG Node = 'rs232_rec2:inst1\|state_rec\[2\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { rs232_rec2:inst1|clkbaud8x~clkctrl rs232_rec2:inst1|state_rec[2] } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 211 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 43.13 % ) " "Info: Total cell delay = 2.776 ns ( 43.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.660 ns ( 56.87 % ) " "Info: Total interconnect delay = 3.660 ns ( 56.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.436 ns" { pin_clk rs232_rec2:inst1|clkbaud8x rs232_rec2:inst1|clkbaud8x~clkctrl rs232_rec2:inst1|state_rec[2] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.436 ns" { pin_clk {} pin_clk~combout {} rs232_rec2:inst1|clkbaud8x {} rs232_rec2:inst1|clkbaud8x~clkctrl {} rs232_rec2:inst1|state_rec[2] {} } { 0.000ns 0.000ns 1.347ns 1.479ns 0.834ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.432 ns" { pin_clk rs232_rec2:inst1|clkbaud8x rs232_rec2:inst1|clkbaud8x~clkctrl rs232_rec2:inst1|rxd_buf[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.432 ns" { pin_clk {} pin_clk~combout {} rs232_rec2:inst1|clkbaud8x {} rs232_rec2:inst1|clkbaud8x~clkctrl {} rs232_rec2:inst1|rxd_buf[0] {} } { 0.000ns 0.000ns 1.347ns 1.479ns 0.830ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.436 ns" { pin_clk rs232_rec2:inst1|clkbaud8x rs232_rec2:inst1|clkbaud8x~clkctrl rs232_rec2:inst1|state_rec[2] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.436 ns" { pin_clk {} pin_clk~combout {} rs232_rec2:inst1|clkbaud8x {} rs232_rec2:inst1|clkbaud8x~clkctrl {} rs232_rec2:inst1|state_rec[2] {} } { 0.000ns 0.000ns 1.347ns 1.479ns 0.834ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 211 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 211 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.586 ns" { rs232_rec2:inst1|state_rec[2] rs232_rec2:inst1|Equal3~42 rs232_rec2:inst1|rxd_buf[7]~634 rs232_rec2:inst1|rxd_buf[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.586 ns" { rs232_rec2:inst1|state_rec[2] {} rs232_rec2:inst1|Equal3~42 {} rs232_rec2:inst1|rxd_buf[7]~634 {} rs232_rec2:inst1|rxd_buf[0] {} } { 0.000ns 1.147ns 0.708ns 0.972ns } { 0.000ns 0.534ns 0.370ns 0.855ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.432 ns" { pin_clk rs232_rec2:inst1|clkbaud8x rs232_rec2:inst1|clkbaud8x~clkctrl rs232_rec2:inst1|rxd_buf[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.432 ns" { pin_clk {} pin_clk~combout {} rs232_rec2:inst1|clkbaud8x {} rs232_rec2:inst1|clkbaud8x~clkctrl {} rs232_rec2:inst1|rxd_buf[0] {} } { 0.000ns 0.000ns 1.347ns 1.479ns 0.830ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.436 ns" { pin_clk rs232_rec2:inst1|clkbaud8x rs232_rec2:inst1|clkbaud8x~clkctrl rs232_rec2:inst1|state_rec[2] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.436 ns" { pin_clk {} pin_clk~combout {} rs232_rec2:inst1|clkbaud8x {} rs232_rec2:inst1|clkbaud8x~clkctrl {} rs232_rec2:inst1|state_rec[2] {} } { 0.000ns 0.000ns 1.347ns 1.479ns 0.834ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "rs232_rec2:inst1\|test_baud pin_rst pin_clk 5.206 ns register " "Info: tsu for register \"rs232_rec2:inst1\|test_baud\" (data pin = \"pin_rst\", clock pin = \"pin_clk\") is 5.206 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.008 ns + Longest pin register " "Info: + Longest pin to register delay is 8.008 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.964 ns) 0.964 ns pin_rst 1 PIN PIN_72 63 " "Info: 1: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = PIN_72; Fanout = 63; PIN Node = 'pin_rst'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_rst } "NODE_NAME" } } { "rs232_rec5.bdf" "" { Schematic "D:/fpga_dev/rs232_rec5/rs232_rec5.bdf" { { 120 16 184 136 "pin_rst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.285 ns) + CELL(0.651 ns) 7.900 ns rs232_rec2:inst1\|test_baud~172 2 COMB LCCOMB_X6_Y6_N12 1 " "Info: 2: + IC(6.285 ns) + CELL(0.651 ns) = 7.900 ns; Loc. = LCCOMB_X6_Y6_N12; Fanout = 1; COMB Node = 'rs232_rec2:inst1\|test_baud~172'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.936 ns" { pin_rst rs232_rec2:inst1|test_baud~172 } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 8.008 ns rs232_rec2:inst1\|test_baud 3 REG LCFF_X6_Y6_N13 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 8.008 ns; Loc. = LCFF_X6_Y6_N13; Fanout = 2; REG Node = 'rs232_rec2:inst1\|test_baud'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { rs232_rec2:inst1|test_baud~172 rs232_rec2:inst1|test_baud } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.723 ns ( 21.52 % ) " "Info: Total cell delay = 1.723 ns ( 21.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.285 ns ( 78.48 % ) " "Info: Total interconnect delay = 6.285 ns ( 78.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.008 ns" { pin_rst rs232_rec2:inst1|test_baud~172 rs232_rec2:inst1|test_baud } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.008 ns" { pin_rst {} pin_rst~combout {} rs232_rec2:inst1|test_baud~172 {} rs232_rec2:inst1|test_baud {} } { 0.000ns 0.000ns 6.285ns 0.000ns } { 0.000ns 0.964ns 0.651ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pin_clk destination 2.762 ns - Shortest register " "Info: - Shortest clock path from clock \"pin_clk\" to destination register is 2.762 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns pin_clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'pin_clk'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_clk } "NODE_NAME" } } { "rs232_rec5.bdf" "" { Schematic "D:/fpga_dev/rs232_rec5/rs232_rec5.bdf" { { 104 16 184 120 "pin_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns pin_clk~clkctrl 2 COMB CLKCTRL_G2 17 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 17; COMB Node = 'pin_clk~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { pin_clk pin_clk~clkctrl } "NODE_NAME" } } { "rs232_rec5.bdf" "" { Schematic "D:/fpga_dev/rs232_rec5/rs232_rec5.bdf" { { 104 16 184 120 "pin_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.813 ns) + CELL(0.666 ns) 2.762 ns rs232_rec2:inst1\|test_baud 3 REG LCFF_X6_Y6_N13 2 " "Info: 3: + IC(0.813 ns) + CELL(0.666 ns) = 2.762 ns; Loc. = LCFF_X6_Y6_N13; Fanout = 2; REG Node = 'rs232_rec2:inst1\|test_baud'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.479 ns" { pin_clk~clkctrl rs232_rec2:inst1|test_baud } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 65.39 % ) " "Info: Total cell delay = 1.806 ns ( 65.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.956 ns ( 34.61 % ) " "Info: Total interconnect delay = 0.956 ns ( 34.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.762 ns" { pin_clk pin_clk~clkctrl rs232_rec2:inst1|test_baud } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.762 ns" { pin_clk {} pin_clk~combout {} pin_clk~clkctrl {} rs232_rec2:inst1|test_baud {} } { 0.000ns 0.000ns 0.143ns 0.813ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.008 ns" { pin_rst rs232_rec2:inst1|test_baud~172 rs232_rec2:inst1|test_baud } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.008 ns" { pin_rst {} pin_rst~combout {} rs232_rec2:inst1|test_baud~172 {} rs232_rec2:inst1|test_baud {} } { 0.000ns 0.000ns 6.285ns 0.000ns } { 0.000ns 0.964ns 0.651ns 0.108ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.762 ns" { pin_clk pin_clk~clkctrl rs232_rec2:inst1|test_baud } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.762 ns" { pin_clk {} pin_clk~combout {} pin_clk~clkctrl {} rs232_rec2:inst1|test_baud {} } { 0.000ns 0.000ns 0.143ns 0.813ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "pin_clk data\[7\] rs232_rec2:inst1\|rec_data\[7\] 13.208 ns register " "Info: tco from clock \"pin_clk\" to destination pin \"data\[7\]\" through register \"rs232_rec2:inst1\|rec_data\[7\]\" is 13.208 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pin_clk source 6.440 ns + Longest register " "Info: + Longest clock path from clock \"pin_clk\" to source register is 6.440 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns pin_clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'pin_clk'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_clk } "NODE_NAME" } } { "rs232_rec5.bdf" "" { Schematic "D:/fpga_dev/rs232_rec5/rs232_rec5.bdf" { { 104 16 184 120 "pin_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.347 ns) + CELL(0.970 ns) 3.457 ns rs232_rec2:inst1\|clkbaud8x 2 REG LCFF_X6_Y6_N17 3 " "Info: 2: + IC(1.347 ns) + CELL(0.970 ns) = 3.457 ns; Loc. = LCFF_X6_Y6_N17; Fanout = 3; REG Node = 'rs232_rec2:inst1\|clkbaud8x'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.317 ns" { pin_clk rs232_rec2:inst1|clkbaud8x } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.479 ns) + CELL(0.000 ns) 4.936 ns rs232_rec2:inst1\|clkbaud8x~clkctrl 3 COMB CLKCTRL_G1 54 " "Info: 3: + IC(1.479 ns) + CELL(0.000 ns) = 4.936 ns; Loc. = CLKCTRL_G1; Fanout = 54; COMB Node = 'rs232_rec2:inst1\|clkbaud8x~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.479 ns" { rs232_rec2:inst1|clkbaud8x rs232_rec2:inst1|clkbaud8x~clkctrl } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.838 ns) + CELL(0.666 ns) 6.440 ns rs232_rec2:inst1\|rec_data\[7\] 4 REG LCFF_X20_Y4_N19 2 " "Info: 4: + IC(0.838 ns) + CELL(0.666 ns) = 6.440 ns; Loc. = LCFF_X20_Y4_N19; Fanout = 2; REG Node = 'rs232_rec2:inst1\|rec_data\[7\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.504 ns" { rs232_rec2:inst1|clkbaud8x~clkctrl rs232_rec2:inst1|rec_data[7] } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 211 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 43.11 % ) " "Info: Total cell delay = 2.776 ns ( 43.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.664 ns ( 56.89 % ) " "Info: Total interconnect delay = 3.664 ns ( 56.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.440 ns" { pin_clk rs232_rec2:inst1|clkbaud8x rs232_rec2:inst1|clkbaud8x~clkctrl rs232_rec2:inst1|rec_data[7] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.440 ns" { pin_clk {} pin_clk~combout {} rs232_rec2:inst1|clkbaud8x {} rs232_rec2:inst1|clkbaud8x~clkctrl {} rs232_rec2:inst1|rec_data[7] {} } { 0.000ns 0.000ns 1.347ns 1.479ns 0.838ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 211 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.464 ns + Longest register pin " "Info: + Longest register to pin delay is 6.464 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rs232_rec2:inst1\|rec_data\[7\] 1 REG LCFF_X20_Y4_N19 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X20_Y4_N19; Fanout = 2; REG Node = 'rs232_rec2:inst1\|rec_data\[7\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rs232_rec2:inst1|rec_data[7] } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 211 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.168 ns) + CELL(3.296 ns) 6.464 ns data\[7\] 2 PIN PIN_57 0 " "Info: 2: + IC(3.168 ns) + CELL(3.296 ns) = 6.464 ns; Loc. = PIN_57; Fanout = 0; PIN Node = 'data\[7\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.464 ns" { rs232_rec2:inst1|rec_data[7] data[7] } "NODE_NAME" } } { "rs232_rec5.bdf" "" { Schematic "D:/fpga_dev/rs232_rec5/rs232_rec5.bdf" { { 312 624 800 328 "data\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.296 ns ( 50.99 % ) " "Info: Total cell delay = 3.296 ns ( 50.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.168 ns ( 49.01 % ) " "Info: Total interconnect delay = 3.168 ns ( 49.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.464 ns" { rs232_rec2:inst1|rec_data[7] data[7] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.464 ns" { rs232_rec2:inst1|rec_data[7] {} data[7] {} } { 0.000ns 3.168ns } { 0.000ns 3.296ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.440 ns" { pin_clk rs232_rec2:inst1|clkbaud8x rs232_rec2:inst1|clkbaud8x~clkctrl rs232_rec2:inst1|rec_data[7] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.440 ns" { pin_clk {} pin_clk~combout {} rs232_rec2:inst1|clkbaud8x {} rs232_rec2:inst1|clkbaud8x~clkctrl {} rs232_rec2:inst1|rec_data[7] {} } { 0.000ns 0.000ns 1.347ns 1.479ns 0.838ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.464 ns" { rs232_rec2:inst1|rec_data[7] data[7] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.464 ns" { rs232_rec2:inst1|rec_data[7] {} data[7] {} } { 0.000ns 3.168ns } { 0.000ns 3.296ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}