rs232_rec5.fnsim.qmsg

VHDL语言实现的穿行通讯

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version " "Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 28 10:25:04 2008 " "Info: Processing started: Fri Mar 28 10:25:04 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off rs232_rec5 -c rs232_rec5 --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off rs232_rec5 -c rs232_rec5 --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rs232_rec2.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file rs232_rec2.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rs232_rec2-arch " "Info: Found design unit 1: rs232_rec2-arch" {  } { { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 28 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 rs232_rec2 " "Info: Found entity 1: rs232_rec2" {  } { { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rs232_rec5.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file rs232_rec5.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 rs232_rec5 " "Info: Found entity 1: rs232_rec5" {  } { { "rs232_rec5.bdf" "" { Schematic "D:/fpga_dev/rs232_rec5/rs232_rec5.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "rs232_rec5 " "Info: Elaborating entity \"rs232_rec5\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "clk rs232_rec2 inst " "Warning: Port \"clk\" of type rs232_rec2 and instance \"inst\" is missing source signal" {  } { { "rs232_rec5.bdf" "" { Schematic "D:/fpga_dev/rs232_rec5/rs232_rec5.bdf" { { 248 -24 176 408 "inst" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rs232_rec2 rs232_rec2:inst1 " "Info: Elaborating entity \"rs232_rec2\" for hierarchy \"rs232_rec2:inst1\"" {  } { { "rs232_rec5.bdf" "inst1" { Schematic "D:/fpga_dev/rs232_rec5/rs232_rec5.bdf" { { 80 248 448 240 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "varTime rs232_rec2.vhd(227) " "Warning (10036): Verilog HDL or VHDL warning at rs232_rec2.vhd(227): object \"varTime\" assigned a value but never read" {  } { { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 227 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "14 " "Info: Inferred 14 megafunctions from design logic" { { "Info" "ILPMS_LPM_MUX_INFERRED" "rs232_rec2:inst1\|Mux0 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"rs232_rec2:inst1\|Mux0\"" {  } { { "rs232_rec2.vhd" "Mux0" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 258 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "rs232_rec2:inst1\|Mux1 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"rs232_rec2:inst1\|Mux1\"" {  } { { "rs232_rec2.vhd" "Mux1" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 258 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "rs232_rec2:inst1\|Mux2 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"rs232_rec2:inst1\|Mux2\"" {  } { { "rs232_rec2.vhd" "Mux2" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 258 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "rs232_rec2:inst1\|Mux3 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"rs232_rec2:inst1\|Mux3\"" {  } { { "rs232_rec2.vhd" "Mux3" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 258 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "rs232_rec2:inst1\|Mux4 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"rs232_rec2:inst1\|Mux4\"" {  } { { "rs232_rec2.vhd" "Mux4" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 258 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "rs232_rec2:inst1\|Mux5 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"rs232_rec2:inst1\|Mux5\"" {  } { { "rs232_rec2.vhd" "Mux5" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 258 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "rs232_rec2:inst1\|Mux6 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"rs232_rec2:inst1\|Mux6\"" {  } { { "rs232_rec2.vhd" "Mux6" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 258 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "rs232_rec2:inst1\|Mux7 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"rs232_rec2:inst1\|Mux7\"" {  } { { "rs232_rec2.vhd" "Mux7" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 258 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "rs232_rec2:inst1\|Mux8 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"rs232_rec2:inst1\|Mux8\"" {  } { { "rs232_rec2.vhd" "Mux8" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 258 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "rs232_rec2:inst1\|Mux9 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"rs232_rec2:inst1\|Mux9\"" {  } { { "rs232_rec2.vhd" "Mux9" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 258 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "rs232_rec2:inst1\|Mux10 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"rs232_rec2:inst1\|Mux10\"" {  } { { "rs232_rec2.vhd" "Mux10" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 258 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "rs232_rec2:inst1\|Mux11 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"rs232_rec2:inst1\|Mux11\"" {  } { { "rs232_rec2.vhd" "Mux11" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 258 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "rs232_rec2:inst1\|Mux12 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"rs232_rec2:inst1\|Mux12\"" {  } { { "rs232_rec2.vhd" "Mux12" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 258 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "rs232_rec2:inst1\|Mux13 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"rs232_rec2:inst1\|Mux13\"" {  } { { "rs232_rec2.vhd" "Mux13" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 258 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/72/quartus/libraries/megafunctions/lpm_mux.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/72/quartus/libraries/megafunctions/lpm_mux.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mux " "Info: Found entity 1: lpm_mux" {  } { { "lpm_mux.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/lpm_mux.tdf" 74 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "rs232_rec2:inst1\|lpm_mux:Mux0 " "Info: Elaborated megafunction instantiation \"rs232_rec2:inst1\|lpm_mux:Mux0\"" {  } { { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 258 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_joc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_joc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_joc " "Info: Found entity 1: mux_joc" {  } { { "db/mux_joc.tdf" "" { Text "D:/fpga_dev/rs232_rec5/db/mux_joc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "rs232_rec2:inst1\|lpm_mux:Mux1 " "Info: Elaborated megafunction instantiation \"rs232_rec2:inst1\|lpm_mux:Mux1\"" {  } { { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 258 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "rs232_rec2:inst1\|lpm_mux:Mux4 " "Info: Elaborated megafunction instantiation \"rs232_rec2:inst1\|lpm_mux:Mux4\"" {  } { { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 258 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "rs232_rec2:inst1\|lpm_mux:Mux13 " "Info: Elaborated megafunction instantiation \"rs232_rec2:inst1\|lpm_mux:Mux13\"" {  } { { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 258 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 2 s Quartus II " "Info: Quartus II Functional Simulation Netlist Generation was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "160 " "Info: Allocated 160 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 28 10:25:07 2008 " "Info: Processing ended: Fri Mar 28 10:25:07 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}