prev_cmp_rs232_rec5.fit.qmsg

VHDL语言实现的穿行通讯

{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.823 ns register register " "Info: Estimated most critical path is register to register delay of 3.823 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rs232_rec2:inst1\|div_reg\[0\] 1 REG LAB_X17_Y5 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X17_Y5; Fanout = 3; REG Node = 'rs232_rec2:inst1\|div_reg\[0\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rs232_rec2:inst1|div_reg[0] } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 81 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.954 ns) + CELL(0.621 ns) 1.575 ns rs232_rec2:inst1\|Add0~193 2 COMB LAB_X18_Y5 2 " "Info: 2: + IC(0.954 ns) + CELL(0.621 ns) = 1.575 ns; Loc. = LAB_X18_Y5; Fanout = 2; COMB Node = 'rs232_rec2:inst1\|Add0~193'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.575 ns" { rs232_rec2:inst1|div_reg[0] rs232_rec2:inst1|Add0~193 } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.661 ns rs232_rec2:inst1\|Add0~195 3 COMB LAB_X18_Y5 2 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.661 ns; Loc. = LAB_X18_Y5; Fanout = 2; COMB Node = 'rs232_rec2:inst1\|Add0~195'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { rs232_rec2:inst1|Add0~193 rs232_rec2:inst1|Add0~195 } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.747 ns rs232_rec2:inst1\|Add0~197 4 COMB LAB_X18_Y5 2 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.747 ns; Loc. = LAB_X18_Y5; Fanout = 2; COMB Node = 'rs232_rec2:inst1\|Add0~197'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { rs232_rec2:inst1|Add0~195 rs232_rec2:inst1|Add0~197 } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.833 ns rs232_rec2:inst1\|Add0~199 5 COMB LAB_X18_Y5 2 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 1.833 ns; Loc. = LAB_X18_Y5; Fanout = 2; COMB Node = 'rs232_rec2:inst1\|Add0~199'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { rs232_rec2:inst1|Add0~197 rs232_rec2:inst1|Add0~199 } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.919 ns rs232_rec2:inst1\|Add0~201 6 COMB LAB_X18_Y5 2 " "Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 1.919 ns; Loc. = LAB_X18_Y5; Fanout = 2; COMB Node = 'rs232_rec2:inst1\|Add0~201'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { rs232_rec2:inst1|Add0~199 rs232_rec2:inst1|Add0~201 } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.005 ns rs232_rec2:inst1\|Add0~203 7 COMB LAB_X18_Y5 2 " "Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 2.005 ns; Loc. = LAB_X18_Y5; Fanout = 2; COMB Node = 'rs232_rec2:inst1\|Add0~203'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { rs232_rec2:inst1|Add0~201 rs232_rec2:inst1|Add0~203 } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.091 ns rs232_rec2:inst1\|Add0~205 8 COMB LAB_X18_Y5 2 " "Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 2.091 ns; Loc. = LAB_X18_Y5; Fanout = 2; COMB Node = 'rs232_rec2:inst1\|Add0~205'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { rs232_rec2:inst1|Add0~203 rs232_rec2:inst1|Add0~205 } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 2.597 ns rs232_rec2:inst1\|Add0~206 9 COMB LAB_X18_Y5 1 " "Info: 9: + IC(0.000 ns) + CELL(0.506 ns) = 2.597 ns; Loc. = LAB_X18_Y5; Fanout = 1; COMB Node = 'rs232_rec2:inst1\|Add0~206'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { rs232_rec2:inst1|Add0~205 rs232_rec2:inst1|Add0~206 } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.467 ns) + CELL(0.651 ns) 3.715 ns rs232_rec2:inst1\|div_reg~282 10 COMB LAB_X17_Y5 1 " "Info: 10: + IC(0.467 ns) + CELL(0.651 ns) = 3.715 ns; Loc. = LAB_X17_Y5; Fanout = 1; COMB Node = 'rs232_rec2:inst1\|div_reg~282'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.118 ns" { rs232_rec2:inst1|Add0~206 rs232_rec2:inst1|div_reg~282 } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.823 ns rs232_rec2:inst1\|div_reg\[7\] 11 REG LAB_X17_Y5 3 " "Info: 11: + IC(0.000 ns) + CELL(0.108 ns) = 3.823 ns; Loc. = LAB_X17_Y5; Fanout = 3; REG Node = 'rs232_rec2:inst1\|div_reg\[7\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { rs232_rec2:inst1|div_reg~282 rs232_rec2:inst1|div_reg[7] } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 81 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.402 ns ( 62.83 % ) " "Info: Total cell delay = 2.402 ns ( 62.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.421 ns ( 37.17 % ) " "Info: Total interconnect delay = 1.421 ns ( 37.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.823 ns" { rs232_rec2:inst1|div_reg[0] rs232_rec2:inst1|Add0~193 rs232_rec2:inst1|Add0~195 rs232_rec2:inst1|Add0~197 rs232_rec2:inst1|Add0~199 rs232_rec2:inst1|Add0~201 rs232_rec2:inst1|Add0~203 rs232_rec2:inst1|Add0~205 rs232_rec2:inst1|Add0~206 rs232_rec2:inst1|div_reg~282 rs232_rec2:inst1|div_reg[7] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X14_Y0 X28_Y14 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X14_Y0 to location X28_Y14" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "12 " "Warning: Found 12 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "pin_txd 0 " "Info: Pin \"pin_txd\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "pin_p 0 " "Info: Pin \"pin_p\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "pin_baud 0 " "Info: Pin \"pin_baud\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "pin_baud_rec 0 " "Info: Pin \"pin_baud_rec\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "data\[7\] 0 " "Info: Pin \"data\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "data\[6\] 0 " "Info: Pin \"data\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "data\[5\] 0 " "Info: Pin \"data\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "data\[4\] 0 " "Info: Pin \"data\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "data\[3\] 0 " "Info: Pin \"data\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "data\[2\] 0 " "Info: Pin \"data\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "data\[1\] 0 " "Info: Pin \"data\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "data\[0\] 0 " "Info: Pin \"data\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/fpga_dev/rs232_rec5/rs232_rec5.fit.smsg " "Info: Generated suppressed messages file D:/fpga_dev/rs232_rec5/rs232_rec5.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 10 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "174 " "Info: Allocated 174 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 31 12:57:40 2008 " "Info: Processing ended: Mon Mar 31 12:57:40 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}