prev_cmp_rs232_rec5.tan.qmsg

VHDL语言实现的穿行通讯

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "rs232_rec2:inst1\|clkbaud8x " "Info: Detected ripple clock \"rs232_rec2:inst1\|clkbaud8x\" as buffer" {  } { { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 42 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "rs232_rec2:inst1\|clkbaud8x" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "pin_clk register rs232_rec2:inst1\|state_rec\[2\] register rs232_rec2:inst1\|state_rec\[3\] 253.16 MHz 3.95 ns Internal " "Info: Clock \"pin_clk\" has Internal fmax of 253.16 MHz between source register \"rs232_rec2:inst1\|state_rec\[2\]\" and destination register \"rs232_rec2:inst1\|state_rec\[3\]\" (period= 3.95 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.686 ns + Longest register register " "Info: + Longest register to register delay is 3.686 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rs232_rec2:inst1\|state_rec\[2\] 1 REG LCFF_X13_Y3_N25 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X13_Y3_N25; Fanout = 5; REG Node = 'rs232_rec2:inst1\|state_rec\[2\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rs232_rec2:inst1|state_rec[2] } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 199 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.786 ns) + CELL(0.202 ns) 0.988 ns rs232_rec2:inst1\|data~895 2 COMB LCCOMB_X13_Y3_N8 3 " "Info: 2: + IC(0.786 ns) + CELL(0.202 ns) = 0.988 ns; Loc. = LCCOMB_X13_Y3_N8; Fanout = 3; COMB Node = 'rs232_rec2:inst1\|data~895'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.988 ns" { rs232_rec2:inst1|state_rec[2] rs232_rec2:inst1|data~895 } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.384 ns) + CELL(0.370 ns) 1.742 ns rs232_rec2:inst1\|state_rec~1000 3 COMB LCCOMB_X13_Y3_N16 3 " "Info: 3: + IC(0.384 ns) + CELL(0.370 ns) = 1.742 ns; Loc. = LCCOMB_X13_Y3_N16; Fanout = 3; COMB Node = 'rs232_rec2:inst1\|state_rec~1000'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.754 ns" { rs232_rec2:inst1|data~895 rs232_rec2:inst1|state_rec~1000 } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.404 ns) + CELL(0.370 ns) 2.516 ns rs232_rec2:inst1\|state_rec~1001 4 COMB LCCOMB_X13_Y3_N12 1 " "Info: 4: + IC(0.404 ns) + CELL(0.370 ns) = 2.516 ns; Loc. = LCCOMB_X13_Y3_N12; Fanout = 1; COMB Node = 'rs232_rec2:inst1\|state_rec~1001'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.774 ns" { rs232_rec2:inst1|state_rec~1000 rs232_rec2:inst1|state_rec~1001 } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.411 ns) + CELL(0.651 ns) 3.578 ns rs232_rec2:inst1\|state_rec~1002 5 COMB LCCOMB_X13_Y3_N28 1 " "Info: 5: + IC(0.411 ns) + CELL(0.651 ns) = 3.578 ns; Loc. = LCCOMB_X13_Y3_N28; Fanout = 1; COMB Node = 'rs232_rec2:inst1\|state_rec~1002'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.062 ns" { rs232_rec2:inst1|state_rec~1001 rs232_rec2:inst1|state_rec~1002 } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.686 ns rs232_rec2:inst1\|state_rec\[3\] 6 REG LCFF_X13_Y3_N29 7 " "Info: 6: + IC(0.000 ns) + CELL(0.108 ns) = 3.686 ns; Loc. = LCFF_X13_Y3_N29; Fanout = 7; REG Node = 'rs232_rec2:inst1\|state_rec\[3\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { rs232_rec2:inst1|state_rec~1002 rs232_rec2:inst1|state_rec[3] } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 199 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.701 ns ( 46.15 % ) " "Info: Total cell delay = 1.701 ns ( 46.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.985 ns ( 53.85 % ) " "Info: Total interconnect delay = 1.985 ns ( 53.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.686 ns" { rs232_rec2:inst1|state_rec[2] rs232_rec2:inst1|data~895 rs232_rec2:inst1|state_rec~1000 rs232_rec2:inst1|state_rec~1001 rs232_rec2:inst1|state_rec~1002 rs232_rec2:inst1|state_rec[3] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.686 ns" { rs232_rec2:inst1|state_rec[2] {} rs232_rec2:inst1|data~895 {} rs232_rec2:inst1|state_rec~1000 {} rs232_rec2:inst1|state_rec~1001 {} rs232_rec2:inst1|state_rec~1002 {} rs232_rec2:inst1|state_rec[3] {} } { 0.000ns 0.786ns 0.384ns 0.404ns 0.411ns 0.000ns } { 0.000ns 0.202ns 0.370ns 0.370ns 0.651ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pin_clk destination 7.237 ns + Shortest register " "Info: + Shortest clock path from clock \"pin_clk\" to destination register is 7.237 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns pin_clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'pin_clk'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_clk } "NODE_NAME" } } { "rs232_rec5.bdf" "" { Schematic "D:/fpga_dev/rs232_rec5/rs232_rec5.bdf" { { 104 16 184 120 "pin_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.445 ns) + CELL(0.970 ns) 3.555 ns rs232_rec2:inst1\|clkbaud8x 2 REG LCFF_X17_Y5_N1 3 " "Info: 2: + IC(1.445 ns) + CELL(0.970 ns) = 3.555 ns; Loc. = LCFF_X17_Y5_N1; Fanout = 3; REG Node = 'rs232_rec2:inst1\|clkbaud8x'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.415 ns" { pin_clk rs232_rec2:inst1|clkbaud8x } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.170 ns) + CELL(0.000 ns) 5.725 ns rs232_rec2:inst1\|clkbaud8x~clkctrl 3 COMB CLKCTRL_G6 48 " "Info: 3: + IC(2.170 ns) + CELL(0.000 ns) = 5.725 ns; Loc. = CLKCTRL_G6; Fanout = 48; COMB Node = 'rs232_rec2:inst1\|clkbaud8x~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.170 ns" { rs232_rec2:inst1|clkbaud8x rs232_rec2:inst1|clkbaud8x~clkctrl } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.846 ns) + CELL(0.666 ns) 7.237 ns rs232_rec2:inst1\|state_rec\[3\] 4 REG LCFF_X13_Y3_N29 7 " "Info: 4: + IC(0.846 ns) + CELL(0.666 ns) = 7.237 ns; Loc. = LCFF_X13_Y3_N29; Fanout = 7; REG Node = 'rs232_rec2:inst1\|state_rec\[3\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.512 ns" { rs232_rec2:inst1|clkbaud8x~clkctrl rs232_rec2:inst1|state_rec[3] } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 199 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 38.36 % ) " "Info: Total cell delay = 2.776 ns ( 38.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.461 ns ( 61.64 % ) " "Info: Total interconnect delay = 4.461 ns ( 61.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.237 ns" { pin_clk rs232_rec2:inst1|clkbaud8x rs232_rec2:inst1|clkbaud8x~clkctrl rs232_rec2:inst1|state_rec[3] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.237 ns" { pin_clk {} pin_clk~combout {} rs232_rec2:inst1|clkbaud8x {} rs232_rec2:inst1|clkbaud8x~clkctrl {} rs232_rec2:inst1|state_rec[3] {} } { 0.000ns 0.000ns 1.445ns 2.170ns 0.846ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pin_clk source 7.237 ns - Longest register " "Info: - Longest clock path from clock \"pin_clk\" to source register is 7.237 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns pin_clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'pin_clk'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_clk } "NODE_NAME" } } { "rs232_rec5.bdf" "" { Schematic "D:/fpga_dev/rs232_rec5/rs232_rec5.bdf" { { 104 16 184 120 "pin_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.445 ns) + CELL(0.970 ns) 3.555 ns rs232_rec2:inst1\|clkbaud8x 2 REG LCFF_X17_Y5_N1 3 " "Info: 2: + IC(1.445 ns) + CELL(0.970 ns) = 3.555 ns; Loc. = LCFF_X17_Y5_N1; Fanout = 3; REG Node = 'rs232_rec2:inst1\|clkbaud8x'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.415 ns" { pin_clk rs232_rec2:inst1|clkbaud8x } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.170 ns) + CELL(0.000 ns) 5.725 ns rs232_rec2:inst1\|clkbaud8x~clkctrl 3 COMB CLKCTRL_G6 48 " "Info: 3: + IC(2.170 ns) + CELL(0.000 ns) = 5.725 ns; Loc. = CLKCTRL_G6; Fanout = 48; COMB Node = 'rs232_rec2:inst1\|clkbaud8x~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.170 ns" { rs232_rec2:inst1|clkbaud8x rs232_rec2:inst1|clkbaud8x~clkctrl } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.846 ns) + CELL(0.666 ns) 7.237 ns rs232_rec2:inst1\|state_rec\[2\] 4 REG LCFF_X13_Y3_N25 5 " "Info: 4: + IC(0.846 ns) + CELL(0.666 ns) = 7.237 ns; Loc. = LCFF_X13_Y3_N25; Fanout = 5; REG Node = 'rs232_rec2:inst1\|state_rec\[2\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.512 ns" { rs232_rec2:inst1|clkbaud8x~clkctrl rs232_rec2:inst1|state_rec[2] } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 199 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 38.36 % ) " "Info: Total cell delay = 2.776 ns ( 38.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.461 ns ( 61.64 % ) " "Info: Total interconnect delay = 4.461 ns ( 61.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.237 ns" { pin_clk rs232_rec2:inst1|clkbaud8x rs232_rec2:inst1|clkbaud8x~clkctrl rs232_rec2:inst1|state_rec[2] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.237 ns" { pin_clk {} pin_clk~combout {} rs232_rec2:inst1|clkbaud8x {} rs232_rec2:inst1|clkbaud8x~clkctrl {} rs232_rec2:inst1|state_rec[2] {} } { 0.000ns 0.000ns 1.445ns 2.170ns 0.846ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.237 ns" { pin_clk rs232_rec2:inst1|clkbaud8x rs232_rec2:inst1|clkbaud8x~clkctrl rs232_rec2:inst1|state_rec[3] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.237 ns" { pin_clk {} pin_clk~combout {} rs232_rec2:inst1|clkbaud8x {} rs232_rec2:inst1|clkbaud8x~clkctrl {} rs232_rec2:inst1|state_rec[3] {} } { 0.000ns 0.000ns 1.445ns 2.170ns 0.846ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.237 ns" { pin_clk rs232_rec2:inst1|clkbaud8x rs232_rec2:inst1|clkbaud8x~clkctrl rs232_rec2:inst1|state_rec[2] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.237 ns" { pin_clk {} pin_clk~combout {} rs232_rec2:inst1|clkbaud8x {} rs232_rec2:inst1|clkbaud8x~clkctrl {} rs232_rec2:inst1|state_rec[2] {} } { 0.000ns 0.000ns 1.445ns 2.170ns 0.846ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 199 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 199 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.686 ns" { rs232_rec2:inst1|state_rec[2] rs232_rec2:inst1|data~895 rs232_rec2:inst1|state_rec~1000 rs232_rec2:inst1|state_rec~1001 rs232_rec2:inst1|state_rec~1002 rs232_rec2:inst1|state_rec[3] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.686 ns" { rs232_rec2:inst1|state_rec[2] {} rs232_rec2:inst1|data~895 {} rs232_rec2:inst1|state_rec~1000 {} rs232_rec2:inst1|state_rec~1001 {} rs232_rec2:inst1|state_rec~1002 {} rs232_rec2:inst1|state_rec[3] {} } { 0.000ns 0.786ns 0.384ns 0.404ns 0.411ns 0.000ns } { 0.000ns 0.202ns 0.370ns 0.370ns 0.651ns 0.108ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.237 ns" { pin_clk rs232_rec2:inst1|clkbaud8x rs232_rec2:inst1|clkbaud8x~clkctrl rs232_rec2:inst1|state_rec[3] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.237 ns" { pin_clk {} pin_clk~combout {} rs232_rec2:inst1|clkbaud8x {} rs232_rec2:inst1|clkbaud8x~clkctrl {} rs232_rec2:inst1|state_rec[3] {} } { 0.000ns 0.000ns 1.445ns 2.170ns 0.846ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.237 ns" { pin_clk rs232_rec2:inst1|clkbaud8x rs232_rec2:inst1|clkbaud8x~clkctrl rs232_rec2:inst1|state_rec[2] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.237 ns" { pin_clk {} pin_clk~combout {} rs232_rec2:inst1|clkbaud8x {} rs232_rec2:inst1|clkbaud8x~clkctrl {} rs232_rec2:inst1|state_rec[2] {} } { 0.000ns 0.000ns 1.445ns 2.170ns 0.846ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "rs232_rec2:inst1\|test_baud pin_rst pin_clk 6.241 ns register " "Info: tsu for register \"rs232_rec2:inst1\|test_baud\" (data pin = \"pin_rst\", clock pin = \"pin_clk\") is 6.241 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.057 ns + Longest pin register " "Info: + Longest pin to register delay is 9.057 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.964 ns) 0.964 ns pin_rst 1 PIN PIN_72 66 " "Info: 1: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = PIN_72; Fanout = 66; PIN Node = 'pin_rst'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_rst } "NODE_NAME" } } { "rs232_rec5.bdf" "" { Schematic "D:/fpga_dev/rs232_rec5/rs232_rec5.bdf" { { 120 16 184 136 "pin_rst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(7.334 ns) + CELL(0.651 ns) 8.949 ns rs232_rec2:inst1\|test_baud~172 2 COMB LCCOMB_X17_Y5_N10 1 " "Info: 2: + IC(7.334 ns) + CELL(0.651 ns) = 8.949 ns; Loc. = LCCOMB_X17_Y5_N10; Fanout = 1; COMB Node = 'rs232_rec2:inst1\|test_baud~172'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.985 ns" { pin_rst rs232_rec2:inst1|test_baud~172 } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 9.057 ns rs232_rec2:inst1\|test_baud 3 REG LCFF_X17_Y5_N11 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 9.057 ns; Loc. = LCFF_X17_Y5_N11; Fanout = 2; REG Node = 'rs232_rec2:inst1\|test_baud'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { rs232_rec2:inst1|test_baud~172 rs232_rec2:inst1|test_baud } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.723 ns ( 19.02 % ) " "Info: Total cell delay = 1.723 ns ( 19.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.334 ns ( 80.98 % ) " "Info: Total interconnect delay = 7.334 ns ( 80.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.057 ns" { pin_rst rs232_rec2:inst1|test_baud~172 rs232_rec2:inst1|test_baud } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.057 ns" { pin_rst {} pin_rst~combout {} rs232_rec2:inst1|test_baud~172 {} rs232_rec2:inst1|test_baud {} } { 0.000ns 0.000ns 7.334ns 0.000ns } { 0.000ns 0.964ns 0.651ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pin_clk destination 2.776 ns - Shortest register " "Info: - Shortest clock path from clock \"pin_clk\" to destination register is 2.776 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns pin_clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'pin_clk'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_clk } "NODE_NAME" } } { "rs232_rec5.bdf" "" { Schematic "D:/fpga_dev/rs232_rec5/rs232_rec5.bdf" { { 104 16 184 120 "pin_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns pin_clk~clkctrl 2 COMB CLKCTRL_G2 17 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 17; COMB Node = 'pin_clk~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { pin_clk pin_clk~clkctrl } "NODE_NAME" } } { "rs232_rec5.bdf" "" { Schematic "D:/fpga_dev/rs232_rec5/rs232_rec5.bdf" { { 104 16 184 120 "pin_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.827 ns) + CELL(0.666 ns) 2.776 ns rs232_rec2:inst1\|test_baud 3 REG LCFF_X17_Y5_N11 2 " "Info: 3: + IC(0.827 ns) + CELL(0.666 ns) = 2.776 ns; Loc. = LCFF_X17_Y5_N11; Fanout = 2; REG Node = 'rs232_rec2:inst1\|test_baud'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.493 ns" { pin_clk~clkctrl rs232_rec2:inst1|test_baud } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 65.06 % ) " "Info: Total cell delay = 1.806 ns ( 65.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.970 ns ( 34.94 % ) " "Info: Total interconnect delay = 0.970 ns ( 34.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.776 ns" { pin_clk pin_clk~clkctrl rs232_rec2:inst1|test_baud } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.776 ns" { pin_clk {} pin_clk~combout {} pin_clk~clkctrl {} rs232_rec2:inst1|test_baud {} } { 0.000ns 0.000ns 0.143ns 0.827ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.057 ns" { pin_rst rs232_rec2:inst1|test_baud~172 rs232_rec2:inst1|test_baud } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.057 ns" { pin_rst {} pin_rst~combout {} rs232_rec2:inst1|test_baud~172 {} rs232_rec2:inst1|test_baud {} } { 0.000ns 0.000ns 7.334ns 0.000ns } { 0.000ns 0.964ns 0.651ns 0.108ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.776 ns" { pin_clk pin_clk~clkctrl rs232_rec2:inst1|test_baud } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.776 ns" { pin_clk {} pin_clk~combout {} pin_clk~clkctrl {} rs232_rec2:inst1|test_baud {} } { 0.000ns 0.000ns 0.143ns 0.827ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "pin_clk pin_txd rs232_rec2:inst1\|txd_reg 13.474 ns register " "Info: tco from clock \"pin_clk\" to destination pin \"pin_txd\" through register \"rs232_rec2:inst1\|txd_reg\" is 13.474 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pin_clk source 7.240 ns + Longest register " "Info: + Longest clock path from clock \"pin_clk\" to source register is 7.240 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns pin_clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'pin_clk'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_clk } "NODE_NAME" } } { "rs232_rec5.bdf" "" { Schematic "D:/fpga_dev/rs232_rec5/rs232_rec5.bdf" { { 104 16 184 120 "pin_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.445 ns) + CELL(0.970 ns) 3.555 ns rs232_rec2:inst1\|clkbaud8x 2 REG LCFF_X17_Y5_N1 3 " "Info: 2: + IC(1.445 ns) + CELL(0.970 ns) = 3.555 ns; Loc. = LCFF_X17_Y5_N1; Fanout = 3; REG Node = 'rs232_rec2:inst1\|clkbaud8x'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.415 ns" { pin_clk rs232_rec2:inst1|clkbaud8x } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.170 ns) + CELL(0.000 ns) 5.725 ns rs232_rec2:inst1\|clkbaud8x~clkctrl 3 COMB CLKCTRL_G6 48 " "Info: 3: + IC(2.170 ns) + CELL(0.000 ns) = 5.725 ns; Loc. = CLKCTRL_G6; Fanout = 48; COMB Node = 'rs232_rec2:inst1\|clkbaud8x~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.170 ns" { rs232_rec2:inst1|clkbaud8x rs232_rec2:inst1|clkbaud8x~clkctrl } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.849 ns) + CELL(0.666 ns) 7.240 ns rs232_rec2:inst1\|txd_reg 4 REG LCFF_X13_Y2_N1 2 " "Info: 4: + IC(0.849 ns) + CELL(0.666 ns) = 7.240 ns; Loc. = LCFF_X13_Y2_N1; Fanout = 2; REG Node = 'rs232_rec2:inst1\|txd_reg'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.515 ns" { rs232_rec2:inst1|clkbaud8x~clkctrl rs232_rec2:inst1|txd_reg } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 281 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 38.34 % ) " "Info: Total cell delay = 2.776 ns ( 38.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.464 ns ( 61.66 % ) " "Info: Total interconnect delay = 4.464 ns ( 61.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.240 ns" { pin_clk rs232_rec2:inst1|clkbaud8x rs232_rec2:inst1|clkbaud8x~clkctrl rs232_rec2:inst1|txd_reg } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.240 ns" { pin_clk {} pin_clk~combout {} rs232_rec2:inst1|clkbaud8x {} rs232_rec2:inst1|clkbaud8x~clkctrl {} rs232_rec2:inst1|txd_reg {} } { 0.000ns 0.000ns 1.445ns 2.170ns 0.849ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 281 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.930 ns + Longest register pin " "Info: + Longest register to pin delay is 5.930 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rs232_rec2:inst1\|txd_reg 1 REG LCFF_X13_Y2_N1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X13_Y2_N1; Fanout = 2; REG Node = 'rs232_rec2:inst1\|txd_reg'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rs232_rec2:inst1|txd_reg } "NODE_NAME" } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 281 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.814 ns) + CELL(3.116 ns) 5.930 ns pin_txd 2 PIN PIN_146 0 " "Info: 2: + IC(2.814 ns) + CELL(3.116 ns) = 5.930 ns; Loc. = PIN_146; Fanout = 0; PIN Node = 'pin_txd'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.930 ns" { rs232_rec2:inst1|txd_reg pin_txd } "NODE_NAME" } } { "rs232_rec5.bdf" "" { Schematic "D:/fpga_dev/rs232_rec5/rs232_rec5.bdf" { { 104 624 800 120 "pin_txd" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.116 ns ( 52.55 % ) " "Info: Total cell delay = 3.116 ns ( 52.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.814 ns ( 47.45 % ) " "Info: Total interconnect delay = 2.814 ns ( 47.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.930 ns" { rs232_rec2:inst1|txd_reg pin_txd } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.930 ns" { rs232_rec2:inst1|txd_reg {} pin_txd {} } { 0.000ns 2.814ns } { 0.000ns 3.116ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.240 ns" { pin_clk rs232_rec2:inst1|clkbaud8x rs232_rec2:inst1|clkbaud8x~clkctrl rs232_rec2:inst1|txd_reg } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.240 ns" { pin_clk {} pin_clk~combout {} rs232_rec2:inst1|clkbaud8x {} rs232_rec2:inst1|clkbaud8x~clkctrl {} rs232_rec2:inst1|txd_reg {} } { 0.000ns 0.000ns 1.445ns 2.170ns 0.849ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.930 ns" { rs232_rec2:inst1|txd_reg pin_txd } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.930 ns" { rs232_rec2:inst1|txd_reg {} pin_txd {} } { 0.000ns 2.814ns } { 0.000ns 3.116ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}