prev_cmp_rs232_rec5.qmsg

VHDL语言实现的穿行通讯

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version " "Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 31 15:41:12 2008 " "Info: Processing started: Mon Mar 31 15:41:12 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off rs232_rec5 -c rs232_rec5 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off rs232_rec5 -c rs232_rec5" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rs232_rec2.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file rs232_rec2.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rs232_rec2-arch " "Info: Found design unit 1: rs232_rec2-arch" {  } { { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 31 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 rs232_rec2 " "Info: Found entity 1: rs232_rec2" {  } { { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rs232_rec5.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file rs232_rec5.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 rs232_rec5 " "Info: Found entity 1: rs232_rec5" {  } { { "rs232_rec5.bdf" "" { Schematic "D:/fpga_dev/rs232_rec5/rs232_rec5.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "rs232_rec5 " "Info: Elaborating entity \"rs232_rec5\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rs232_rec2 rs232_rec2:inst1 " "Info: Elaborating entity \"rs232_rec2\" for hierarchy \"rs232_rec2:inst1\"" {  } { { "rs232_rec5.bdf" "inst1" { Schematic "D:/fpga_dev/rs232_rec5/rs232_rec5.bdf" { { 80 248 448 272 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rs232_rec2:inst1\|sam_end data_in GND " "Warning (14130): Reduced register \"rs232_rec2:inst1\|sam_end\" with stuck data_in port to stuck value GND" {  } { { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 199 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "rs232_rec2:inst1\|test_baud_rec rs232_rec2:inst1\|clkbaud_rec " "Info: Duplicate register \"rs232_rec2:inst1\|test_baud_rec\" merged to single register \"rs232_rec2:inst1\|clkbaud_rec\"" {  } { { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 22 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "rs232_rec2:inst1\|test_baud8x_p rs232_rec2:inst1\|clkbaud_tras " "Info: Duplicate register \"rs232_rec2:inst1\|test_baud8x_p\" merged to single register \"rs232_rec2:inst1\|clkbaud_tras\"" {  } { { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 23 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "rs232_rec2:inst1\|data\[7\] rs232_rec2:inst1\|rec_data\[7\] " "Info: Duplicate register \"rs232_rec2:inst1\|data\[7\]\" merged to single register \"rs232_rec2:inst1\|rec_data\[7\]\"" {  } { { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 211 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "rs232_rec2:inst1\|data\[6\] rs232_rec2:inst1\|rec_data\[6\] " "Info: Duplicate register \"rs232_rec2:inst1\|data\[6\]\" merged to single register \"rs232_rec2:inst1\|rec_data\[6\]\"" {  } { { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 211 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "rs232_rec2:inst1\|data\[5\] rs232_rec2:inst1\|rec_data\[5\] " "Info: Duplicate register \"rs232_rec2:inst1\|data\[5\]\" merged to single register \"rs232_rec2:inst1\|rec_data\[5\]\"" {  } { { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 211 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "rs232_rec2:inst1\|data\[4\] rs232_rec2:inst1\|rec_data\[4\] " "Info: Duplicate register \"rs232_rec2:inst1\|data\[4\]\" merged to single register \"rs232_rec2:inst1\|rec_data\[4\]\"" {  } { { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 211 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "rs232_rec2:inst1\|data\[3\] rs232_rec2:inst1\|rec_data\[3\] " "Info: Duplicate register \"rs232_rec2:inst1\|data\[3\]\" merged to single register \"rs232_rec2:inst1\|rec_data\[3\]\"" {  } { { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 211 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "rs232_rec2:inst1\|data\[2\] rs232_rec2:inst1\|rec_data\[2\] " "Info: Duplicate register \"rs232_rec2:inst1\|data\[2\]\" merged to single register \"rs232_rec2:inst1\|rec_data\[2\]\"" {  } { { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 211 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "rs232_rec2:inst1\|data\[1\] rs232_rec2:inst1\|rec_data\[1\] " "Info: Duplicate register \"rs232_rec2:inst1\|data\[1\]\" merged to single register \"rs232_rec2:inst1\|rec_data\[1\]\"" {  } { { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 211 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "rs232_rec2:inst1\|data\[0\] rs232_rec2:inst1\|rec_data\[0\] " "Info: Duplicate register \"rs232_rec2:inst1\|data\[0\]\" merged to single register \"rs232_rec2:inst1\|rec_data\[0\]\"" {  } { { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 211 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 341 -1 0 } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 45 -1 0 } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 341 -1 0 } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 341 -1 0 } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 341 -1 0 } } { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 341 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0}
{ "Critical Warning" "WFTM_FTM_POWER_UP_HIGH_IGNORED_GROUP" "" "Critical Warning: Ignored Power-Up Level option on the following registers" { { "Critical Warning" "WFTM_FTM_CORE_REG_POWER_UP_HIGH_IGNORED" "rs232_rec2:inst1\|txd_buf\[0\] Low " "Critical Warning: Register rs232_rec2:inst1\|txd_buf\[0\] will power up to Low" {  } { { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 341 -1 0 } }  } 1 0 "Register %1!s! will power up to %2!s!" 0 0 "" 0} { "Critical Warning" "WFTM_FTM_CORE_REG_POWER_UP_HIGH_IGNORED" "rs232_rec2:inst1\|txd_buf\[2\] Low " "Critical Warning: Register rs232_rec2:inst1\|txd_buf\[2\] will power up to Low" {  } { { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 341 -1 0 } }  } 1 0 "Register %1!s! will power up to %2!s!" 0 0 "" 0} { "Critical Warning" "WFTM_FTM_CORE_REG_POWER_UP_HIGH_IGNORED" "rs232_rec2:inst1\|txd_buf\[6\] High " "Critical Warning: Register rs232_rec2:inst1\|txd_buf\[6\] will power up to High" {  } { { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 341 -1 0 } }  } 1 0 "Register %1!s! will power up to %2!s!" 0 0 "" 0} { "Critical Warning" "WFTM_FTM_CORE_REG_POWER_UP_HIGH_IGNORED" "rs232_rec2:inst1\|txd_buf\[7\] High " "Critical Warning: Register rs232_rec2:inst1\|txd_buf\[7\] will power up to High" {  } { { "rs232_rec2.vhd" "" { Text "D:/fpga_dev/rs232_rec5/rs232_rec2.vhd" 341 -1 0 } }  } 1 0 "Register %1!s! will power up to %2!s!" 0 0 "" 0}  } {  } 1 0 "Ignored Power-Up Level option on the following registers" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "135 " "Info: Implemented 135 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "12 " "Info: Implemented 12 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "120 " "Info: Implemented 120 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "161 " "Info: Allocated 161 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 31 15:41:18 2008 " "Info: Processing ended: Mon Mar 31 15:41:18 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}