rs232_rec5.hier_info

VHDL语言实现的穿行通讯

|rs232_rec5
pin_txd <= rs232_rec2:inst1.txd
pin_clk => rs232_rec2:inst1.clk
pin_rst => rs232_rec2:inst1.rst
pin_rxd => rs232_rec2:inst1.rxd
pin_p <= rs232_rec2:inst1.test_baud
pin_baud <= rs232_rec2:inst1.test_baud8x_p
pin_baud_rec <= rs232_rec2:inst1.test_baud_rec
data[0] <= rs232_rec2:inst1.data[0]
data[1] <= rs232_rec2:inst1.data[1]
data[2] <= rs232_rec2:inst1.data[2]
data[3] <= rs232_rec2:inst1.data[3]
data[4] <= rs232_rec2:inst1.data[4]
data[5] <= rs232_rec2:inst1.data[5]
data[6] <= rs232_rec2:inst1.data[6]
data[7] <= rs232_rec2:inst1.data[7]


|rs232_rec5|rs232_rec2:inst1
clk => div_reg[15].CLK
clk => div_reg[14].CLK
clk => div_reg[13].CLK
clk => div_reg[12].CLK
clk => div_reg[11].CLK
clk => div_reg[10].CLK
clk => div_reg[9].CLK
clk => div_reg[8].CLK
clk => div_reg[7].CLK
clk => div_reg[6].CLK
clk => div_reg[5].CLK
clk => div_reg[4].CLK
clk => div_reg[3].CLK
clk => div_reg[2].CLK
clk => div_reg[1].CLK
clk => div_reg[0].CLK
clk => clkbaud8x.CLK
clk => test_baud~reg0.CLK
rst => div_reg[0].ACLR
rst => div_reg[1].ACLR
rst => div_reg[2].ACLR
rst => div_reg[3].ACLR
rst => div_reg[4].ACLR
rst => div_reg[5].ACLR
rst => div_reg[6].ACLR
rst => div_reg[7].ACLR
rst => div_reg[8].ACLR
rst => div_reg[9].ACLR
rst => div_reg[10].ACLR
rst => div_reg[11].ACLR
rst => div_reg[12].ACLR
rst => div_reg[13].ACLR
rst => div_reg[14].ACLR
rst => div_reg[15].ACLR
rst => clkbaud8x.ACLR
rst => div8_tras_reg[0].ACLR
rst => div8_tras_reg[1].ACLR
rst => div8_tras_reg[2].ACLR
rst => div8_rec_reg[0].ACLR
rst => div8_rec_reg[1].ACLR
rst => div8_rec_reg[2].ACLR
rst => trasstart.PRESET
rst => txd_buf[0].ACLR
rst => txd_buf[1].ACLR
rst => txd_buf[2].ACLR
rst => txd_buf[3].ACLR
rst => txd_buf[4].PRESET
rst => txd_buf[5].PRESET
rst => txd_buf[6].PRESET
rst => txd_buf[7].PRESET
rst => state_tras[0].ACLR
rst => state_tras[1].ACLR
rst => state_tras[2].ACLR
rst => state_tras[3].ACLR
rst => txd_reg.PRESET
rst => sam_begin.ACLR
rst => sam_end.ACLR
rst => rxd_reg1.ACLR
rst => rxd_reg2.ACLR
rst => rxd_buf[7].ACLR
rst => rxd_buf[6].ACLR
rst => rxd_buf[5].ACLR
rst => rxd_buf[4].ACLR
rst => rxd_buf[3].ACLR
rst => rxd_buf[2].ACLR
rst => rxd_buf[1].ACLR
rst => rxd_buf[0].ACLR
rst => state_rec[3].ACLR
rst => state_rec[2].ACLR
rst => state_rec[1].ACLR
rst => state_rec[0].ACLR
rst => recstart.ACLR
rst => recstart_tmp.ACLR
rst => test_baud~reg0.ENA
rst => clkbaud_rec.ENA
rst => send_write~reg0.ENA
rst => test_baud_rec~reg0.ENA
rst => clkbaud_tras.ENA
rst => test_baud8x_p~reg0.ENA
rst => sam_times[1].ENA
rst => sam_times[0].ENA
rst => values[2].ENA
rst => values[1].ENA
rst => values[0].ENA
rst => rec_write~reg0.ENA
rst => rec_data[7]~reg0.ENA
rst => rec_data[6]~reg0.ENA
rst => rec_data[5]~reg0.ENA
rst => rec_data[4]~reg0.ENA
rst => rec_data[3]~reg0.ENA
rst => rec_data[2]~reg0.ENA
rst => rec_data[1]~reg0.ENA
rst => rec_data[0]~reg0.ENA
rst => data[7]~reg0.ENA
rst => data[6]~reg0.ENA
rst => data[5]~reg0.ENA
rst => data[4]~reg0.ENA
rst => data[3]~reg0.ENA
rst => data[2]~reg0.ENA
rst => data[1]~reg0.ENA
rst => data[0]~reg0.ENA
rxd => rxd_reg1.DATAIN
rxd => values~5.OUTPUTSELECT
rxd => values~4.OUTPUTSELECT
rxd => values~3.OUTPUTSELECT
txd <= txd_reg.DB_MAX_OUTPUT_PORT_TYPE
send_data[0] => txd_buf~7.DATAB
send_data[1] => txd_buf~6.DATAB
send_data[2] => txd_buf~5.DATAB
send_data[3] => txd_buf~4.DATAB
send_data[4] => txd_buf~3.DATAB
send_data[5] => txd_buf~2.DATAB
send_data[6] => txd_buf~1.DATAB
send_data[7] => txd_buf~0.DATAB
send_read => Mux21.IN3
send_read => Mux21.IN4
send_read => Mux21.IN5
send_read => Mux21.IN6
send_read => Mux21.IN7
send_read => trasstart~0.DATAA
send_read => process4~0.IN0
send_read => process5~0.IN0
send_write <= send_write~reg0.DB_MAX_OUTPUT_PORT_TYPE
rec_data[0] <= rec_data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rec_data[1] <= rec_data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rec_data[2] <= rec_data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rec_data[3] <= rec_data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rec_data[4] <= rec_data[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rec_data[5] <= rec_data[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rec_data[6] <= rec_data[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rec_data[7] <= rec_data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rec_write <= rec_write~reg0.DB_MAX_OUTPUT_PORT_TYPE
rec_read => process5~0.IN1
rec_read => process4~0.IN1
test_baud_rec <= test_baud_rec~reg0.DB_MAX_OUTPUT_PORT_TYPE
test_baud8x_p <= test_baud8x_p~reg0.DB_MAX_OUTPUT_PORT_TYPE
test_baud <= test_baud~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[0] <= data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[1] <= data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[2] <= data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[3] <= data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[4] <= data[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[5] <= data[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[6] <= data[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[7] <= data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE