📄 rs232_rec2.vhd.bak
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY rs232_rec2 IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
rxd : IN std_logic; --串行数据接收端
txd : OUT std_logic; --串行数据发送端
-- led : out std_logic_vector(7 downto 0);
send_data :in std_logic_vector(7 downto 0);
send_read :in std_logic;
send_write :out std_logic:='0';
rec_data :out std_logic_vector(7 downto 0);
rec_write :out std_logic:='0';
rec_read :in std_logic;
test_baud_rec : OUT std_logic;
test_baud8x_p : OUT std_logic;--tras
test_baud : OUT std_logic;
data :out std_logic_vector(7 downto 0)
);
END rs232_rec2;
ARCHITECTURE arch OF rs232_rec2 IS
--//////////////////inner reg////////////////////
SIGNAL div_reg : std_logic_vector(15 DOWNTO 0);--分频计数器，分频值由波特率决定。分频后得到频率8倍波特率的时钟
SIGNAL div8_tras_reg : std_logic_vector(2 DOWNTO 0);--该寄存器的计数值对应发送时当前位于的时隙数
SIGNAL div8_rec_reg : std_logic_vector(2 DOWNTO 0); --寄存器的计数值对应接收时当前位于的时隙数
SIGNAL state_tras : std_logic_vector(3 DOWNTO 0); -- 发送状态寄存器
SIGNAL state_rec : std_logic_vector(3 DOWNTO 0); -- 接受状态寄存器
SIGNAL clkbaud_tras : std_logic; --以波特率为频率的发送使能信号
-------------------------------------------------
SIGNAL clkbaud_rec : std_logic; --以波特率为频率的接受使能信号
SIGNAL clkbaud8x : std_logic; --以8倍波特率为频率的时钟，它的作用是将发送或接受一个bit的时钟周期分为8个时隙
SIGNAL recstart : std_logic; -- 开始发送标志
SIGNAL recstart_tmp : std_logic; --开始接受标志
SIGNAL trasstart : std_logic:='1';
SIGNAL rxd_reg1 : std_logic; --接收寄存器1
SIGNAL rxd_reg2 : std_logic; --接收寄存器2，因为接收数据为异步信号，故用两级缓存
SIGNAL txd_reg : std_logic; --发送寄存器
SIGNAL rxd_buf : std_logic_vector(7 DOWNTO 0);--接受数据缓存
SIGNAL txd_buf : std_logic_vector(7 DOWNTO 0):="00110101";--发送数据缓存
SIGNAL send_state : std_logic_vector(2 DOWNTO 0);--每次按键给PC发送"Welcome"字符串，这是发送状态寄存器
SIGNAL key_entry2 : std_logic; --确定有键按下标志
--//////////////////////////////////////////////
CONSTANT div_par : std_logic_vector(15 DOWNTO 0) := ---"0000000000011011"; --"0000000101000101"; 11011-27,101000101-325
--"0000010100010110";
"0000000010100011";--19200*8
--分频参数，其值由对应的波特率计算而得，按此参数分频的时钟频率是波倍特率的8倍，此处值对应4800的波特率，即分频出的时钟频率是9600*8
SIGNAL txd_xhdl3 : std_logic;
SIGNAL buf : std_logic_vector(7 DOWNTO 0);
------------------------------
--used for sample
-- SIGNAL sam_times : std_logic_vector(1 DOWNTO 0):="00";
-- SIGNAL values : std_logic_vector(2 DOWNTO 0):="000";
-- SIGNAL not_trasstart : std_logic;
-- signal send_read : std_logic;
-- signal send_write : std_logic;
-- signal rec_write : std_logic;
-- signal rec_read : std_logic;
BEGIN
txd <= txd_xhdl3;
txd_xhdl3 <= txd_reg ;
-- led<=rxd_buf;
--trasstart<=not_trasstart;
PROCESS(clk,rst)
BEGIN
IF (NOT rst = '1') THEN
div_reg <= "0000000000000000";
ELSIF(clk'EVENT AND clk='1')THEN
IF (div_reg = div_par - "0000000000000001") THEN
div_reg <= "0000000000000000";
ELSE
div_reg <= div_reg + "0000000000000001";
END IF;
END IF;
END PROCESS;
PROCESS(clk,rst) --分频得到8倍波特率的时钟
BEGIN
-- test_baud8x_p<=NOT clk;
IF (NOT rst = '1') THEN
clkbaud8x <= '0';
ELSIF(clk'EVENT AND clk='1')THEN
IF (div_reg = div_par - "0000000000000001") THEN
clkbaud8x <= NOT clkbaud8x;
test_baud<=clkbaud8x;
END IF;
END IF;
END PROCESS;
-- test_baud8x_p<=clkbaud8x;
PROCESS(clkbaud8x,rst)
BEGIN
IF (NOT rst = '1') THEN
div8_rec_reg <= "000";
ELSE IF(clkbaud8x'EVENT AND clkbaud8x = '1') THEN
-----------------------------------------------------------
IF (recstart = '1') THEN --接收开始标志 origin
div8_rec_reg <= div8_rec_reg + "001";--接收开始后，时隙数在8倍波特率的时钟下加1循环
---------------------------------------
---------------------------------------
IF (div8_rec_reg = "111") THEN
clkbaud_rec <= '1'; ---在第7个时隙，接收使能信号有效，将数据打入
test_baud_rec<='1';
ELSE
clkbaud_rec <= '0';
test_baud_rec<='0';
END IF;
---------------------------------------
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(clkbaud8x,rst)
BEGIN
IF (NOT rst = '1') THEN
div8_tras_reg <= "000";
ELSE IF(clkbaud8x'EVENT AND clkbaud8x = '1') THEN
----------------------------------------------
-- if(trasstart = '0' )then
-- clkbaud_tras <= '0';
-- else
IF (trasstart = '1') THEN --origin
div8_tras_reg <= div8_tras_reg + "001";--发送开始后，时隙数在8倍波特率的时钟下加1循环
----------------------------------------------
----------------------------------------------
IF (div8_tras_reg = "111") THEN
clkbaud_tras <= '1'; --在第7个时隙，发送使能信号有效，将数据发出
test_baud8x_p<='1';
--div8_tras_reg <= "000";
ELSE
clkbaud_tras <= '0';
test_baud8x_p<='0';
END IF;
------------------------------------------------
------------------------------------------------
-- end if;
END IF;
END IF;
END IF;
END PROCESS;
-- PROCESS(div8_rec_reg)
-- BEGIN
-- IF (div8_rec_reg = "011") THEN
-- clkbaud_rec <= '1'; ---在第7个时隙，接收使能信号有效，将数据打入
-- test_baud_rec<='1';
-- ELSE
-- clkbaud_rec <= '0';
-- test_baud_rec<='0';
-- END IF;
-- END PROCESS;
-- PROCESS(div8_tras_reg)
-- BEGIN
-- IF (div8_tras_reg = "111") THEN
-- clkbaud_tras <= '1'; --在第7个时隙，发送使能信号有效，将数据发出
-- test_baud8x_p<='1';
-- ELSE
-- clkbaud_tras <= '0';
-- test_baud8x_p<='0';
-- END IF;
-- END PROCESS;
PROCESS(clkbaud8x,rst) --接受PC机的数据
--variable rxd_buf : std_logic_vector(7 DOWNTO 0);
variable sam_times : std_logic_vector(1 DOWNTO 0):="00";
variable values : std_logic_vector(2 DOWNTO 0):="000";
variable sam_begin : std_logic;
variable sam_end : std_logic;
BEGIN
IF (NOT rst = '1') THEN
rxd_reg1 <= '0';
rxd_reg2 <= '0';
rxd_buf <= "00000000";
state_rec <= "0000";
recstart <= '0';
recstart_tmp <= '0';
sam_begin:='0';
sam_end:='0';
ELSE IF(clkbaud8x'EVENT AND clkbaud8x = '1') THEN
if(rec_read='1' and send_read='1')then
rec_write<='0';
end if;
rxd_reg1 <= rxd;
rxd_reg2 <= rxd_reg1;
IF (state_rec = "0000") THEN
IF (recstart_tmp = '1') THEN
recstart <= '1';
sam_times:="00";
values:="000";
recstart_tmp <= '0';
state_rec <= state_rec + "0001";
ELSE
IF ((NOT rxd_reg1 AND rxd_reg2) = '1') THEN --检测到起始位的下降沿，进入接受状态
recstart_tmp <= '1';
--rec_data<="00001111";
--data<="00001111";
END IF;
END IF;
ELSE
IF (state_rec >= "0001" AND state_rec<="1000") THEN
IF (clkbaud_rec = '1') THEN
sam_begin:='1';
end if;
-------------------------------------------
-- sample 3 times
if(sam_begin='1') then
case sam_times is
when "00"=>
if rxd='0' then
values:=values+"000";
else
values:=values+"001";
end if;
sam_times:=sam_times+"01";
when "01"=>
if rxd='0' then
values:=values+"000";
else
values:=values+"001";
end if;
sam_times:=sam_times+"01";
when "10"=>
if rxd='0' then
values:=values+"000";
else
values:=values+"001";
end if;
if values<"001" then
rxd_buf(7)<='0';
end if;
if values>="010" then
rxd_buf(7)<='1';
end if;
sam_begin:='0';
sam_end:='1';
sam_times:="00";
values:="000";
when others => null;
end case;
end if; --if(sam_begin='1')
if(sam_end='1') then
rxd_buf(6 DOWNTO 0)<= rxd_buf(7 DOWNTO 1);
state_rec <= state_rec + "0001";
sam_end:='0';
end if;
--sam_times<=sam_times+"01";
-------------------------------------------
-- END IF;
ELSE
IF (state_rec = "1001") THEN --stop bit
IF (clkbaud_rec = '1') THEN
state_rec <="0000";
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