rs232_rec5.map.rpt

VHDL语言实现的穿行通讯

+---------------------------------------------+---------+
; Estimated Total logic elements              ; 103     ;
;                                             ;         ;
; Total combinational functions               ; 103     ;
; Logic element usage by number of LUT inputs ;         ;
;     -- 4 input functions                    ; 48      ;
;     -- 3 input functions                    ; 21      ;
;     -- <=2 input functions                  ; 34      ;
;                                             ;         ;
; Logic elements by mode                      ;         ;
;     -- normal mode                          ; 88      ;
;     -- arithmetic mode                      ; 15      ;
;                                             ;         ;
; Total registers                             ; 72      ;
;     -- Dedicated logic registers            ; 72      ;
;     -- I/O registers                        ; 0       ;
;                                             ;         ;
; I/O pins                                    ; 15      ;
; Maximum fan-out node                        ; pin_rst ;
; Maximum fan-out                             ; 63      ;
; Total fan-out                               ; 568     ;
; Average fan-out                             ; 2.99    ;
+---------------------------------------------+---------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                  ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name          ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------+--------------+
; |rs232_rec5                ; 103 (0)           ; 72 (0)       ; 0           ; 0            ; 0       ; 0         ; 15   ; 0            ; |rs232_rec5                  ; work         ;
;    |rs232_rec2:inst1|      ; 103 (103)         ; 72 (72)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |rs232_rec5|rs232_rec2:inst1 ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                                 ;
+----------------------------------------+-------------------------------------------+
; Register name                          ; Reason for Removal                        ;
+----------------------------------------+-------------------------------------------+
; rs232_rec2:inst1|sam_end               ; Stuck at GND due to stuck port data_in    ;
; rs232_rec2:inst1|test_baud_rec         ; Merged with rs232_rec2:inst1|clkbaud_rec  ;
; rs232_rec2:inst1|test_baud8x_p         ; Merged with rs232_rec2:inst1|clkbaud_tras ;
; rs232_rec2:inst1|data[7]               ; Merged with rs232_rec2:inst1|rec_data[7]  ;
; rs232_rec2:inst1|data[6]               ; Merged with rs232_rec2:inst1|rec_data[6]  ;
; rs232_rec2:inst1|data[5]               ; Merged with rs232_rec2:inst1|rec_data[5]  ;
; rs232_rec2:inst1|data[4]               ; Merged with rs232_rec2:inst1|rec_data[4]  ;
; rs232_rec2:inst1|data[3]               ; Merged with rs232_rec2:inst1|rec_data[3]  ;
; rs232_rec2:inst1|data[2]               ; Merged with rs232_rec2:inst1|rec_data[2]  ;
; rs232_rec2:inst1|data[1]               ; Merged with rs232_rec2:inst1|rec_data[1]  ;
; rs232_rec2:inst1|data[0]               ; Merged with rs232_rec2:inst1|rec_data[0]  ;
; Total Number of Removed Registers = 11 ;                                           ;
+----------------------------------------+-------------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 72    ;
; Number of registers using Synchronous Clear  ; 1     ;
; Number of registers using Synchronous Load   ; 1     ;
; Number of registers using Asynchronous Clear ; 54    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 34    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; rs232_rec2:inst1|txd_reg               ; 2       ;
; rs232_rec2:inst1|trasstart             ; 13      ;
; rs232_rec2:inst1|txd_buf[4]            ; 1       ;
; rs232_rec2:inst1|txd_buf[5]            ; 1       ;
; rs232_rec2:inst1|txd_buf[6]            ; 1       ;
; rs232_rec2:inst1|txd_buf[7]            ; 2       ;
; Total number of inverted registers = 6 ;         ;
+----------------------------------------+---------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                        ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output              ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------+
; 11:1               ; 2 bits    ; 14 LEs        ; 2 LEs                ; 12 LEs                 ; Yes        ; |rs232_rec5|rs232_rec2:inst1|txd_buf[1] ;
; 8:1                ; 3 bits    ; 15 LEs        ; 3 LEs                ; 12 LEs                 ; Yes        ; |rs232_rec5|rs232_rec2:inst1|values[2]  ;
; 11:1               ; 5 bits    ; 35 LEs        ; 5 LEs                ; 30 LEs                 ; Yes        ; |rs232_rec5|rs232_rec2:inst1|txd_buf[0] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version
    Info: Processing started: Mon Mar 31 15:41:58 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off rs232_rec5 -c rs232_rec5
Info: Found 2 design units, including 1 entities, in source file rs232_rec2.vhd
    Info: Found design unit 1: rs232_rec2-arch
    Info: Found entity 1: rs232_rec2
Info: Found 1 design units, including 1 entities, in source file rs232_rec5.bdf
    Info: Found entity 1: rs232_rec5
Info: Elaborating entity "rs232_rec5" for the top level hierarchy
Info: Elaborating entity "rs232_rec2" for hierarchy "rs232_rec2:inst1"
Warning (14130): Reduced register "rs232_rec2:inst1|sam_end" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "rs232_rec2:inst1|test_baud_rec" merged to single register "rs232_rec2:inst1|clkbaud_rec"
    Info: Duplicate register "rs232_rec2:inst1|test_baud8x_p" merged to single register "rs232_rec2:inst1|clkbaud_tras"
    Info: Duplicate register "rs232_rec2:inst1|data[7]" merged to single register "rs232_rec2:inst1|rec_data[7]"
    Info: Duplicate register "rs232_rec2:inst1|data[6]" merged to single register "rs232_rec2:inst1|rec_data[6]"
    Info: Duplicate register "rs232_rec2:inst1|data[5]" merged to single register "rs232_rec2:inst1|rec_data[5]"
    Info: Duplicate register "rs232_rec2:inst1|data[4]" merged to single register "rs232_rec2:inst1|rec_data[4]"
    Info: Duplicate register "rs232_rec2:inst1|data[3]" merged to single register "rs232_rec2:inst1|rec_data[3]"
    Info: Duplicate register "rs232_rec2:inst1|data[2]" merged to single register "rs232_rec2:inst1|rec_data[2]"
    Info: Duplicate register "rs232_rec2:inst1|data[1]" merged to single register "rs232_rec2:inst1|rec_data[1]"
    Info: Duplicate register "rs232_rec2:inst1|data[0]" merged to single register "rs232_rec2:inst1|rec_data[0]"
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Critical Warning: Ignored Power-Up Level option on the following registers
    Critical Warning: Register rs232_rec2:inst1|txd_buf[0] will power up to Low
    Critical Warning: Register rs232_rec2:inst1|txd_buf[2] will power up to Low
    Critical Warning: Register rs232_rec2:inst1|txd_buf[6] will power up to High
    Critical Warning: Register rs232_rec2:inst1|txd_buf[7] will power up to High
Info: Implemented 135 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 12 output pins
    Info: Implemented 120 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings
    Info: Allocated 162 megabytes of memory during processing
    Info: Processing ended: Mon Mar 31 15:42:03 2008
    Info: Elapsed time: 00:00:05