water.tan.rpt

与其他流水灯设计不一样

; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; coff1[10] ; coff1[2]  ; clk        ; clk      ; None                        ; None                      ; 3.325 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; coff1[10] ; coff1[0]  ; clk        ; clk      ; None                        ; None                      ; 3.325 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; coff1[10] ; coff1[1]  ; clk        ; clk      ; None                        ; None                      ; 3.325 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; coff1[10] ; coff1[4]  ; clk        ; clk      ; None                        ; None                      ; 3.325 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; coff1[10] ; coff1[5]  ; clk        ; clk      ; None                        ; None                      ; 3.325 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; coff2[10] ; coff2[3]  ; clk        ; clk      ; None                        ; None                      ; 3.320 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; coff2[10] ; coff2[2]  ; clk        ; clk      ; None                        ; None                      ; 3.320 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; coff2[10] ; coff2[0]  ; clk        ; clk      ; None                        ; None                      ; 3.320 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; coff2[10] ; coff2[1]  ; clk        ; clk      ; None                        ; None                      ; 3.320 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; coff2[10] ; coff2[4]  ; clk        ; clk      ; None                        ; None                      ; 3.320 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; coff2[10] ; coff2[5]  ; clk        ; clk      ; None                        ; None                      ; 3.320 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; coff1[9]  ; coff1[11] ; clk        ; clk      ; None                        ; None                      ; 3.295 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; coff1[9]  ; coff1[10] ; clk        ; clk      ; None                        ; None                      ; 3.295 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; coff1[9]  ; coff1[6]  ; clk        ; clk      ; None                        ; None                      ; 3.295 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; coff1[9]  ; coff1[7]  ; clk        ; clk      ; None                        ; None                      ; 3.295 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; coff1[9]  ; coff1[8]  ; clk        ; clk      ; None                        ; None                      ; 3.295 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; coff1[9]  ; coff1[9]  ; clk        ; clk      ; None                        ; None                      ; 3.295 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;           ;           ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+-----------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+


+---------------------------------------------------------------------------------+
; tco                                                                             ;
+-------+--------------+------------+------------------+-------------+------------+
; Slack ; Required tco ; Actual tco ; From             ; To          ; From Clock ;
+-------+--------------+------------+------------------+-------------+------------+
; N/A   ; None         ; 11.906 ns  ; ledwater[6]~reg0 ; ledwater[6] ; clk        ;
; N/A   ; None         ; 11.897 ns  ; ledwater[7]~reg0 ; ledwater[7] ; clk        ;
; N/A   ; None         ; 11.859 ns  ; ledwater[2]~reg0 ; ledwater[2] ; clk        ;
; N/A   ; None         ; 11.854 ns  ; ledwater[0]~reg0 ; ledwater[0] ; clk        ;
; N/A   ; None         ; 11.851 ns  ; ledwater[1]~reg0 ; ledwater[1] ; clk        ;
; N/A   ; None         ; 11.468 ns  ; ledwater[5]~reg0 ; ledwater[5] ; clk        ;
; N/A   ; None         ; 11.468 ns  ; ledwater[4]~reg0 ; ledwater[4] ; clk        ;
; N/A   ; None         ; 11.464 ns  ; ledwater[3]~reg0 ; ledwater[3] ; clk        ;
+-------+--------------+------------+------------------+-------------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Tue Nov 11 17:05:45 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off water -c water --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "clock" as buffer
Info: Clock "clk" has Internal fmax of 217.44 MHz between source register "coff2[3]" and destination register "coff2[3]" (period= 4.599 ns)
    Info: + Longest register to register delay is 4.338 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y14_N7; Fanout = 4; REG Node = 'coff2[3]'
        Info: 2: + IC(1.240 ns) + CELL(0.442 ns) = 1.682 ns; Loc. = LC_X8_Y13_N7; Fanout = 1; COMB Node = 'LessThan1~152'
        Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 1.978 ns; Loc. = LC_X8_Y13_N8; Fanout = 13; COMB Node = 'LessThan1~154'
        Info: 4: + IC(1.248 ns) + CELL(1.112 ns) = 4.338 ns; Loc. = LC_X8_Y14_N7; Fanout = 4; REG Node = 'coff2[3]'
        Info: Total cell delay = 1.668 ns ( 38.45 % )
        Info: Total interconnect delay = 2.670 ns ( 61.55 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.954 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 25; CLK Node = 'clk'
            Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X8_Y14_N7; Fanout = 4; REG Node = 'coff2[3]'
            Info: Total cell delay = 2.180 ns ( 73.80 % )
            Info: Total interconnect delay = 0.774 ns ( 26.20 % )
        Info: - Longest clock path from clock "clk" to source register is 2.954 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 25; CLK Node = 'clk'
            Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X8_Y14_N7; Fanout = 4; REG Node = 'coff2[3]'
            Info: Total cell delay = 2.180 ns ( 73.80 % )
            Info: Total interconnect delay = 0.774 ns ( 26.20 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "clk" to destination pin "ledwater[6]" through register "ledwater[6]~reg0" is 11.906 ns
    Info: + Longest clock path from clock "clk" to source register is 7.972 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 25; CLK Node = 'clk'
        Info: 2: + IC(0.774 ns) + CELL(0.935 ns) = 3.178 ns; Loc. = LC_X7_Y14_N6; Fanout = 13; REG Node = 'clock'
        Info: 3: + IC(4.083 ns) + CELL(0.711 ns) = 7.972 ns; Loc. = LC_X1_Y18_N8; Fanout = 1; REG Node = 'ledwater[6]~reg0'
        Info: Total cell delay = 3.115 ns ( 39.07 % )
        Info: Total interconnect delay = 4.857 ns ( 60.93 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 3.710 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y18_N8; Fanout = 1; REG Node = 'ledwater[6]~reg0'
        Info: 2: + IC(1.586 ns) + CELL(2.124 ns) = 3.710 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'ledwater[6]'
        Info: Total cell delay = 2.124 ns ( 57.25 % )
        Info: Total interconnect delay = 1.586 ns ( 42.75 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Allocated 98 megabytes of memory during processing
    Info: Processing ended: Tue Nov 11 17:05:46 2008
    Info: Elapsed time: 00:00:01