water.v

来自「与其他流水灯设计不一样」· Verilog 代码 · 共 50 行

module water(
                clk,
                ledwater
                );
        input clk;
        output [7:0]ledwater;
        
        reg [11:0] coff1,coff2;
        reg clock;
        reg [7:0] ledwater;
        reg [3:0] state;
        
        
        always @(posedge clk)
                begin
                        if(coff1>=1000)
                        begin
                                coff1 = 10'b0;
                                if(coff2>=1000)
                                        begin coff2=10'b0000000000; clock = ~clock; end
                                else
                                        coff2 = coff2 + 10'b0000000001;
                        end
                        else coff1 = coff1 + 10'b0000000001;
                end
                
        always @(posedge clock)
                begin state = state + 4'b0001; 
                        case(state)
                        4'b0000: ledwater <= 8'b11111110;
                        4'b0001: ledwater <= 8'b11111101;
                        4'b0010: ledwater <= 8'b11111011;
                        4'b0011: ledwater <= 8'b11110111;
                        4'b0100: ledwater <= 8'b11101111;
                        4'b0101: ledwater <= 8'b11011111;
                        4'b0110: ledwater <= 8'b10111111;
                        4'b0111: ledwater <= 8'b01111111;
                        
                        4'b1000: ledwater <= 8'b01111111;
                        4'b1001: ledwater <= 8'b10111111;
                        4'b1010: ledwater <= 8'b11011111;
                        4'b1011: ledwater <= 8'b11101111;
                        4'b1100: ledwater <= 8'b11110111;
                        4'b1101: ledwater <= 8'b11111011;
                        4'b1110: ledwater <= 8'b11111101;
                        4'b1111: ledwater <= 8'b11111110;
                        default: state = 4'b0000;
                        endcase
                end
endmodule