paobiao.tan.rpt

给出了数字跑表的源代码

; N/A           ; None        ; -1.774 ns ; PAUSE ; MSL[2]~reg0 ; CLK      ;
; N/A           ; None        ; -2.048 ns ; PAUSE ; MSL[0]~reg0 ; CLK      ;
; N/A           ; None        ; -2.048 ns ; PAUSE ; MSL[3]~reg0 ; CLK      ;
; N/A           ; None        ; -2.048 ns ; PAUSE ; MSL[1]~reg0 ; CLK      ;
; N/A           ; None        ; -2.048 ns ; PAUSE ; cn1         ; CLK      ;
; N/A           ; None        ; -2.101 ns ; PAUSE ; MSH[2]~reg0 ; CLK      ;
; N/A           ; None        ; -2.569 ns ; PAUSE ; MSH[0]~reg0 ; CLK      ;
; N/A           ; None        ; -2.569 ns ; PAUSE ; MSH[1]~reg0 ; CLK      ;
; N/A           ; None        ; -2.569 ns ; PAUSE ; MSH[3]~reg0 ; CLK      ;
+---------------+-------------+-----------+-------+-------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Tue Oct 21 15:01:47 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off paobiao -c paobiao --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "cn2" as buffer
    Info: Detected ripple clock "cn1" as buffer
Info: Clock "CLK" Internal fmax is restricted to 422.12 MHz between source register "MSL[0]~reg0" and destination register "MSH[0]~reg0"
    Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.019 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y17_N8; Fanout = 6; REG Node = 'MSL[0]~reg0'
            Info: 2: + IC(0.400 ns) + CELL(0.366 ns) = 0.766 ns; Loc. = LC_X1_Y17_N2; Fanout = 3; COMB Node = 'Equal0~90'
            Info: 3: + IC(0.134 ns) + CELL(0.075 ns) = 0.975 ns; Loc. = LC_X1_Y17_N3; Fanout = 3; COMB Node = 'MSH[0]~360'
            Info: 4: + IC(0.339 ns) + CELL(0.705 ns) = 2.019 ns; Loc. = LC_X1_Y17_N9; Fanout = 6; REG Node = 'MSH[0]~reg0'
            Info: Total cell delay = 1.146 ns ( 56.76 % )
            Info: Total interconnect delay = 0.873 ns ( 43.24 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CLK" to destination register is 3.059 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 9; CLK Node = 'CLK'
                Info: 2: + IC(1.689 ns) + CELL(0.542 ns) = 3.059 ns; Loc. = LC_X1_Y17_N9; Fanout = 6; REG Node = 'MSH[0]~reg0'
                Info: Total cell delay = 1.370 ns ( 44.79 % )
                Info: Total interconnect delay = 1.689 ns ( 55.21 % )
            Info: - Longest clock path from clock "CLK" to source register is 3.059 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 9; CLK Node = 'CLK'
                Info: 2: + IC(1.689 ns) + CELL(0.542 ns) = 3.059 ns; Loc. = LC_X1_Y17_N8; Fanout = 6; REG Node = 'MSL[0]~reg0'
                Info: Total cell delay = 1.370 ns ( 44.79 % )
                Info: Total interconnect delay = 1.689 ns ( 55.21 % )
        Info: + Micro clock to output delay of source is 0.156 ns
        Info: + Micro setup delay of destination is 0.010 ns
Info: tsu for register "MSH[0]~reg0" (data pin = "PAUSE", clock pin = "CLK") is 2.679 ns
    Info: + Longest pin to register delay is 5.728 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_L20; Fanout = 7; PIN Node = 'PAUSE'
        Info: 2: + IC(3.673 ns) + CELL(0.183 ns) = 4.684 ns; Loc. = LC_X1_Y17_N3; Fanout = 3; COMB Node = 'MSH[0]~360'
        Info: 3: + IC(0.339 ns) + CELL(0.705 ns) = 5.728 ns; Loc. = LC_X1_Y17_N9; Fanout = 6; REG Node = 'MSH[0]~reg0'
        Info: Total cell delay = 1.716 ns ( 29.96 % )
        Info: Total interconnect delay = 4.012 ns ( 70.04 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 3.059 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 9; CLK Node = 'CLK'
        Info: 2: + IC(1.689 ns) + CELL(0.542 ns) = 3.059 ns; Loc. = LC_X1_Y17_N9; Fanout = 6; REG Node = 'MSH[0]~reg0'
        Info: Total cell delay = 1.370 ns ( 44.79 % )
        Info: Total interconnect delay = 1.689 ns ( 55.21 % )
Info: tco from clock "CLK" to destination pin "MH[1]" through register "MH[1]~reg0" is 16.140 ns
    Info: + Longest clock path from clock "CLK" to source register is 10.793 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 9; CLK Node = 'CLK'
        Info: 2: + IC(1.689 ns) + CELL(0.698 ns) = 3.215 ns; Loc. = LC_X1_Y17_N5; Fanout = 10; REG Node = 'cn1'
        Info: 3: + IC(2.773 ns) + CELL(0.698 ns) = 6.686 ns; Loc. = LC_X8_Y9_N0; Fanout = 9; REG Node = 'cn2'
        Info: 4: + IC(3.565 ns) + CELL(0.542 ns) = 10.793 ns; Loc. = LC_X36_Y1_N9; Fanout = 4; REG Node = 'MH[1]~reg0'
        Info: Total cell delay = 2.766 ns ( 25.63 % )
        Info: Total interconnect delay = 8.027 ns ( 74.37 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 5.191 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X36_Y1_N9; Fanout = 4; REG Node = 'MH[1]~reg0'
        Info: 2: + IC(2.787 ns) + CELL(2.404 ns) = 5.191 ns; Loc. = PIN_D9; Fanout = 0; PIN Node = 'MH[1]'
        Info: Total cell delay = 2.404 ns ( 46.31 % )
        Info: Total interconnect delay = 2.787 ns ( 53.69 % )
Info: th for register "MSL[2]~reg0" (data pin = "PAUSE", clock pin = "CLK") is -1.774 ns
    Info: + Longest clock path from clock "CLK" to destination register is 3.059 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 9; CLK Node = 'CLK'
        Info: 2: + IC(1.689 ns) + CELL(0.542 ns) = 3.059 ns; Loc. = LC_X2_Y17_N2; Fanout = 5; REG Node = 'MSL[2]~reg0'
        Info: Total cell delay = 1.370 ns ( 44.79 % )
        Info: Total interconnect delay = 1.689 ns ( 55.21 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 4.933 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_L20; Fanout = 7; PIN Node = 'PAUSE'
        Info: 2: + IC(3.882 ns) + CELL(0.223 ns) = 4.933 ns; Loc. = LC_X2_Y17_N2; Fanout = 5; REG Node = 'MSL[2]~reg0'
        Info: Total cell delay = 1.051 ns ( 21.31 % )
        Info: Total interconnect delay = 3.882 ns ( 78.69 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Allocated 99 megabytes of memory during processing
    Info: Processing ended: Tue Oct 21 15:01:48 2008
    Info: Elapsed time: 00:00:01