📄 paobiao.tan.qmsg
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{ "Info" "ITDB_TH_RESULT" "MSL\[2\]~reg0 PAUSE CLK -1.774 ns register " "Info: th for register \"MSL\[2\]~reg0\" (data pin = \"PAUSE\", clock pin = \"CLK\") is -1.774 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.059 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 3.059 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_M20 9 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 9; CLK Node = 'CLK'" { } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "paobiao.v" "" { Text "D:/Program Files/quartus/Design/paobiao/paobiao.v" 3 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.689 ns) + CELL(0.542 ns) 3.059 ns MSL\[2\]~reg0 2 REG LC_X2_Y17_N2 5 " "Info: 2: + IC(1.689 ns) + CELL(0.542 ns) = 3.059 ns; Loc. = LC_X2_Y17_N2; Fanout = 5; REG Node = 'MSL\[2\]~reg0'" { } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "2.231 ns" { CLK MSL[2]~reg0 } "NODE_NAME" } } { "paobiao.v" "" { Text "D:/Program Files/quartus/Design/paobiao/paobiao.v" 16 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 44.79 % ) " "Info: Total cell delay = 1.370 ns ( 44.79 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.689 ns ( 55.21 % ) " "Info: Total interconnect delay = 1.689 ns ( 55.21 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "3.059 ns" { CLK MSL[2]~reg0 } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.059 ns" { CLK CLK~out0 MSL[2]~reg0 } { 0.000ns 0.000ns 1.689ns } { 0.000ns 0.828ns 0.542ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" { } { { "paobiao.v" "" { Text "D:/Program Files/quartus/Design/paobiao/paobiao.v" 16 0 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.933 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.933 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns PAUSE 1 PIN PIN_L20 7 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_L20; Fanout = 7; PIN Node = 'PAUSE'" { } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { PAUSE } "NODE_NAME" } } { "paobiao.v" "" { Text "D:/Program Files/quartus/Design/paobiao/paobiao.v" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.882 ns) + CELL(0.223 ns) 4.933 ns MSL\[2\]~reg0 2 REG LC_X2_Y17_N2 5 " "Info: 2: + IC(3.882 ns) + CELL(0.223 ns) = 4.933 ns; Loc. = LC_X2_Y17_N2; Fanout = 5; REG Node = 'MSL\[2\]~reg0'" { } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "4.105 ns" { PAUSE MSL[2]~reg0 } "NODE_NAME" } } { "paobiao.v" "" { Text "D:/Program Files/quartus/Design/paobiao/paobiao.v" 16 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.051 ns ( 21.31 % ) " "Info: Total cell delay = 1.051 ns ( 21.31 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.882 ns ( 78.69 % ) " "Info: Total interconnect delay = 3.882 ns ( 78.69 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "4.933 ns" { PAUSE MSL[2]~reg0 } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "4.933 ns" { PAUSE PAUSE~out0 MSL[2]~reg0 } { 0.000ns 0.000ns 3.882ns } { 0.000ns 0.828ns 0.223ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "3.059 ns" { CLK MSL[2]~reg0 } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.059 ns" { CLK CLK~out0 MSL[2]~reg0 } { 0.000ns 0.000ns 1.689ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "4.933 ns" { PAUSE MSL[2]~reg0 } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "4.933 ns" { PAUSE PAUSE~out0 MSL[2]~reg0 } { 0.000ns 0.000ns 3.882ns } { 0.000ns 0.828ns 0.223ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "99 " "Info: Allocated 99 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 21 15:01:48 2008 " "Info: Processing ended: Tue Oct 21 15:01:48 2008" { } { } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
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