paobiao.tan.qmsg

给出了数字跑表的源代码

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "cn2 " "Info: Detected ripple clock \"cn2\" as buffer" {  } { { "paobiao.v" "" { Text "D:/Program Files/quartus/Design/paobiao/paobiao.v" 8 -1 0 } } { "d:/program files/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus/bin/Assignment Editor.qase" 1 { { 0 "cn2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cn1 " "Info: Detected ripple clock \"cn1\" as buffer" {  } { { "paobiao.v" "" { Text "D:/Program Files/quartus/Design/paobiao/paobiao.v" 8 -1 0 } } { "d:/program files/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus/bin/Assignment Editor.qase" 1 { { 0 "cn1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK register register MSL\[0\]~reg0 MSH\[0\]~reg0 422.12 MHz Internal " "Info: Clock \"CLK\" Internal fmax is restricted to 422.12 MHz between source register \"MSL\[0\]~reg0\" and destination register \"MSH\[0\]~reg0\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.369 ns " "Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.019 ns + Longest register register " "Info: + Longest register to register delay is 2.019 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns MSL\[0\]~reg0 1 REG LC_X1_Y17_N8 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y17_N8; Fanout = 6; REG Node = 'MSL\[0\]~reg0'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { MSL[0]~reg0 } "NODE_NAME" } } { "paobiao.v" "" { Text "D:/Program Files/quartus/Design/paobiao/paobiao.v" 16 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.366 ns) 0.766 ns Equal0~90 2 COMB LC_X1_Y17_N2 3 " "Info: 2: + IC(0.400 ns) + CELL(0.366 ns) = 0.766 ns; Loc. = LC_X1_Y17_N2; Fanout = 3; COMB Node = 'Equal0~90'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "0.766 ns" { MSL[0]~reg0 Equal0~90 } "NODE_NAME" } } { "paobiao.v" "" { Text "D:/Program Files/quartus/Design/paobiao/paobiao.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.134 ns) + CELL(0.075 ns) 0.975 ns MSH\[0\]~360 3 COMB LC_X1_Y17_N3 3 " "Info: 3: + IC(0.134 ns) + CELL(0.075 ns) = 0.975 ns; Loc. = LC_X1_Y17_N3; Fanout = 3; COMB Node = 'MSH\[0\]~360'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "0.209 ns" { Equal0~90 MSH[0]~360 } "NODE_NAME" } } { "paobiao.v" "" { Text "D:/Program Files/quartus/Design/paobiao/paobiao.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.339 ns) + CELL(0.705 ns) 2.019 ns MSH\[0\]~reg0 4 REG LC_X1_Y17_N9 6 " "Info: 4: + IC(0.339 ns) + CELL(0.705 ns) = 2.019 ns; Loc. = LC_X1_Y17_N9; Fanout = 6; REG Node = 'MSH\[0\]~reg0'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "1.044 ns" { MSH[0]~360 MSH[0]~reg0 } "NODE_NAME" } } { "paobiao.v" "" { Text "D:/Program Files/quartus/Design/paobiao/paobiao.v" 16 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.146 ns ( 56.76 % ) " "Info: Total cell delay = 1.146 ns ( 56.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.873 ns ( 43.24 % ) " "Info: Total interconnect delay = 0.873 ns ( 43.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "2.019 ns" { MSL[0]~reg0 Equal0~90 MSH[0]~360 MSH[0]~reg0 } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "2.019 ns" { MSL[0]~reg0 Equal0~90 MSH[0]~360 MSH[0]~reg0 } { 0.000ns 0.400ns 0.134ns 0.339ns } { 0.000ns 0.366ns 0.075ns 0.705ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.059 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 3.059 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_M20 9 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 9; CLK Node = 'CLK'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "paobiao.v" "" { Text "D:/Program Files/quartus/Design/paobiao/paobiao.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.689 ns) + CELL(0.542 ns) 3.059 ns MSH\[0\]~reg0 2 REG LC_X1_Y17_N9 6 " "Info: 2: + IC(1.689 ns) + CELL(0.542 ns) = 3.059 ns; Loc. = LC_X1_Y17_N9; Fanout = 6; REG Node = 'MSH\[0\]~reg0'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "2.231 ns" { CLK MSH[0]~reg0 } "NODE_NAME" } } { "paobiao.v" "" { Text "D:/Program Files/quartus/Design/paobiao/paobiao.v" 16 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 44.79 % ) " "Info: Total cell delay = 1.370 ns ( 44.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.689 ns ( 55.21 % ) " "Info: Total interconnect delay = 1.689 ns ( 55.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "3.059 ns" { CLK MSH[0]~reg0 } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.059 ns" { CLK CLK~out0 MSH[0]~reg0 } { 0.000ns 0.000ns 1.689ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.059 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 3.059 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_M20 9 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 9; CLK Node = 'CLK'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "paobiao.v" "" { Text "D:/Program Files/quartus/Design/paobiao/paobiao.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.689 ns) + CELL(0.542 ns) 3.059 ns MSL\[0\]~reg0 2 REG LC_X1_Y17_N8 6 " "Info: 2: + IC(1.689 ns) + CELL(0.542 ns) = 3.059 ns; Loc. = LC_X1_Y17_N8; Fanout = 6; REG Node = 'MSL\[0\]~reg0'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "2.231 ns" { CLK MSL[0]~reg0 } "NODE_NAME" } } { "paobiao.v" "" { Text "D:/Program Files/quartus/Design/paobiao/paobiao.v" 16 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 44.79 % ) " "Info: Total cell delay = 1.370 ns ( 44.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.689 ns ( 55.21 % ) " "Info: Total interconnect delay = 1.689 ns ( 55.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "3.059 ns" { CLK MSL[0]~reg0 } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.059 ns" { CLK CLK~out0 MSL[0]~reg0 } { 0.000ns 0.000ns 1.689ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "3.059 ns" { CLK MSH[0]~reg0 } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.059 ns" { CLK CLK~out0 MSH[0]~reg0 } { 0.000ns 0.000ns 1.689ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "3.059 ns" { CLK MSL[0]~reg0 } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.059 ns" { CLK CLK~out0 MSL[0]~reg0 } { 0.000ns 0.000ns 1.689ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "paobiao.v" "" { Text "D:/Program Files/quartus/Design/paobiao/paobiao.v" 16 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "paobiao.v" "" { Text "D:/Program Files/quartus/Design/paobiao/paobiao.v" 16 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "2.019 ns" { MSL[0]~reg0 Equal0~90 MSH[0]~360 MSH[0]~reg0 } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "2.019 ns" { MSL[0]~reg0 Equal0~90 MSH[0]~360 MSH[0]~reg0 } { 0.000ns 0.400ns 0.134ns 0.339ns } { 0.000ns 0.366ns 0.075ns 0.705ns } "" } } { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "3.059 ns" { CLK MSH[0]~reg0 } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.059 ns" { CLK CLK~out0 MSH[0]~reg0 } { 0.000ns 0.000ns 1.689ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "3.059 ns" { CLK MSL[0]~reg0 } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.059 ns" { CLK CLK~out0 MSL[0]~reg0 } { 0.000ns 0.000ns 1.689ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { MSH[0]~reg0 } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { MSH[0]~reg0 } {  } {  } "" } } { "paobiao.v" "" { Text "D:/Program Files/quartus/Design/paobiao/paobiao.v" 16 0 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "MSH\[0\]~reg0 PAUSE CLK 2.679 ns register " "Info: tsu for register \"MSH\[0\]~reg0\" (data pin = \"PAUSE\", clock pin = \"CLK\") is 2.679 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.728 ns + Longest pin register " "Info: + Longest pin to register delay is 5.728 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns PAUSE 1 PIN PIN_L20 7 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_L20; Fanout = 7; PIN Node = 'PAUSE'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { PAUSE } "NODE_NAME" } } { "paobiao.v" "" { Text "D:/Program Files/quartus/Design/paobiao/paobiao.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.673 ns) + CELL(0.183 ns) 4.684 ns MSH\[0\]~360 2 COMB LC_X1_Y17_N3 3 " "Info: 2: + IC(3.673 ns) + CELL(0.183 ns) = 4.684 ns; Loc. = LC_X1_Y17_N3; Fanout = 3; COMB Node = 'MSH\[0\]~360'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "3.856 ns" { PAUSE MSH[0]~360 } "NODE_NAME" } } { "paobiao.v" "" { Text "D:/Program Files/quartus/Design/paobiao/paobiao.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.339 ns) + CELL(0.705 ns) 5.728 ns MSH\[0\]~reg0 3 REG LC_X1_Y17_N9 6 " "Info: 3: + IC(0.339 ns) + CELL(0.705 ns) = 5.728 ns; Loc. = LC_X1_Y17_N9; Fanout = 6; REG Node = 'MSH\[0\]~reg0'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "1.044 ns" { MSH[0]~360 MSH[0]~reg0 } "NODE_NAME" } } { "paobiao.v" "" { Text "D:/Program Files/quartus/Design/paobiao/paobiao.v" 16 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.716 ns ( 29.96 % ) " "Info: Total cell delay = 1.716 ns ( 29.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.012 ns ( 70.04 % ) " "Info: Total interconnect delay = 4.012 ns ( 70.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "5.728 ns" { PAUSE MSH[0]~360 MSH[0]~reg0 } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "5.728 ns" { PAUSE PAUSE~out0 MSH[0]~360 MSH[0]~reg0 } { 0.000ns 0.000ns 3.673ns 0.339ns } { 0.000ns 0.828ns 0.183ns 0.705ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "paobiao.v" "" { Text "D:/Program Files/quartus/Design/paobiao/paobiao.v" 16 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.059 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 3.059 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_M20 9 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 9; CLK Node = 'CLK'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "paobiao.v" "" { Text "D:/Program Files/quartus/Design/paobiao/paobiao.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.689 ns) + CELL(0.542 ns) 3.059 ns MSH\[0\]~reg0 2 REG LC_X1_Y17_N9 6 " "Info: 2: + IC(1.689 ns) + CELL(0.542 ns) = 3.059 ns; Loc. = LC_X1_Y17_N9; Fanout = 6; REG Node = 'MSH\[0\]~reg0'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "2.231 ns" { CLK MSH[0]~reg0 } "NODE_NAME" } } { "paobiao.v" "" { Text "D:/Program Files/quartus/Design/paobiao/paobiao.v" 16 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 44.79 % ) " "Info: Total cell delay = 1.370 ns ( 44.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.689 ns ( 55.21 % ) " "Info: Total interconnect delay = 1.689 ns ( 55.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "3.059 ns" { CLK MSH[0]~reg0 } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.059 ns" { CLK CLK~out0 MSH[0]~reg0 } { 0.000ns 0.000ns 1.689ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "5.728 ns" { PAUSE MSH[0]~360 MSH[0]~reg0 } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "5.728 ns" { PAUSE PAUSE~out0 MSH[0]~360 MSH[0]~reg0 } { 0.000ns 0.000ns 3.673ns 0.339ns } { 0.000ns 0.828ns 0.183ns 0.705ns } "" } } { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "3.059 ns" { CLK MSH[0]~reg0 } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.059 ns" { CLK CLK~out0 MSH[0]~reg0 } { 0.000ns 0.000ns 1.689ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK MH\[1\] MH\[1\]~reg0 16.140 ns register " "Info: tco from clock \"CLK\" to destination pin \"MH\[1\]\" through register \"MH\[1\]~reg0\" is 16.140 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 10.793 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 10.793 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_M20 9 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 9; CLK Node = 'CLK'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "paobiao.v" "" { Text "D:/Program Files/quartus/Design/paobiao/paobiao.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.689 ns) + CELL(0.698 ns) 3.215 ns cn1 2 REG LC_X1_Y17_N5 10 " "Info: 2: + IC(1.689 ns) + CELL(0.698 ns) = 3.215 ns; Loc. = LC_X1_Y17_N5; Fanout = 10; REG Node = 'cn1'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "2.387 ns" { CLK cn1 } "NODE_NAME" } } { "paobiao.v" "" { Text "D:/Program Files/quartus/Design/paobiao/paobiao.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.773 ns) + CELL(0.698 ns) 6.686 ns cn2 3 REG LC_X8_Y9_N0 9 " "Info: 3: + IC(2.773 ns) + CELL(0.698 ns) = 6.686 ns; Loc. = LC_X8_Y9_N0; Fanout = 9; REG Node = 'cn2'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "3.471 ns" { cn1 cn2 } "NODE_NAME" } } { "paobiao.v" "" { Text "D:/Program Files/quartus/Design/paobiao/paobiao.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.565 ns) + CELL(0.542 ns) 10.793 ns MH\[1\]~reg0 4 REG LC_X36_Y1_N9 4 " "Info: 4: + IC(3.565 ns) + CELL(0.542 ns) = 10.793 ns; Loc. = LC_X36_Y1_N9; Fanout = 4; REG Node = 'MH\[1\]~reg0'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "4.107 ns" { cn2 MH[1]~reg0 } "NODE_NAME" } } { "paobiao.v" "" { Text "D:/Program Files/quartus/Design/paobiao/paobiao.v" 59 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.766 ns ( 25.63 % ) " "Info: Total cell delay = 2.766 ns ( 25.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.027 ns ( 74.37 % ) " "Info: Total interconnect delay = 8.027 ns ( 74.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "10.793 ns" { CLK cn1 cn2 MH[1]~reg0 } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "10.793 ns" { CLK CLK~out0 cn1 cn2 MH[1]~reg0 } { 0.000ns 0.000ns 1.689ns 2.773ns 3.565ns } { 0.000ns 0.828ns 0.698ns 0.698ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "paobiao.v" "" { Text "D:/Program Files/quartus/Design/paobiao/paobiao.v" 59 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.191 ns + Longest register pin " "Info: + Longest register to pin delay is 5.191 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns MH\[1\]~reg0 1 REG LC_X36_Y1_N9 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X36_Y1_N9; Fanout = 4; REG Node = 'MH\[1\]~reg0'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { MH[1]~reg0 } "NODE_NAME" } } { "paobiao.v" "" { Text "D:/Program Files/quartus/Design/paobiao/paobiao.v" 59 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.787 ns) + CELL(2.404 ns) 5.191 ns MH\[1\] 2 PIN PIN_D9 0 " "Info: 2: + IC(2.787 ns) + CELL(2.404 ns) = 5.191 ns; Loc. = PIN_D9; Fanout = 0; PIN Node = 'MH\[1\]'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "5.191 ns" { MH[1]~reg0 MH[1] } "NODE_NAME" } } { "paobiao.v" "" { Text "D:/Program Files/quartus/Design/paobiao/paobiao.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.404 ns ( 46.31 % ) " "Info: Total cell delay = 2.404 ns ( 46.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.787 ns ( 53.69 % ) " "Info: Total interconnect delay = 2.787 ns ( 53.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "5.191 ns" { MH[1]~reg0 MH[1] } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "5.191 ns" { MH[1]~reg0 MH[1] } { 0.000ns 2.787ns } { 0.000ns 2.404ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "10.793 ns" { CLK cn1 cn2 MH[1]~reg0 } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "10.793 ns" { CLK CLK~out0 cn1 cn2 MH[1]~reg0 } { 0.000ns 0.000ns 1.689ns 2.773ns 3.565ns } { 0.000ns 0.828ns 0.698ns 0.698ns 0.542ns } "" } } { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "5.191 ns" { MH[1]~reg0 MH[1] } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "5.191 ns" { MH[1]~reg0 MH[1] } { 0.000ns 2.787ns } { 0.000ns 2.404ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}