paobiao.fit.smsg

给出了数字跑表的源代码

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Tue Oct 21 15:01:24 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off paobiao -c paobiao
Info: Automatically selected device EP1S10F484C5 for design paobiao
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 62 of 62 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP1S20F484C5 is compatible
Info: Fitter converted 1 user pins into dedicated programming pins
    Info: Pin ~DATA0~ is reserved at location L8
Warning: No exact pin location assignment(s) for 27 pins of 27 total pins
    Info: Pin MSH[0] not assigned to an exact location on the device
    Info: Pin MSH[1] not assigned to an exact location on the device
    Info: Pin MSH[2] not assigned to an exact location on the device
    Info: Pin MSH[3] not assigned to an exact location on the device
    Info: Pin MSL[0] not assigned to an exact location on the device
    Info: Pin MSL[1] not assigned to an exact location on the device
    Info: Pin MSL[2] not assigned to an exact location on the device
    Info: Pin MSL[3] not assigned to an exact location on the device
    Info: Pin SH[0] not assigned to an exact location on the device
    Info: Pin SH[1] not assigned to an exact location on the device
    Info: Pin SH[2] not assigned to an exact location on the device
    Info: Pin SH[3] not assigned to an exact location on the device
    Info: Pin SL[0] not assigned to an exact location on the device
    Info: Pin SL[1] not assigned to an exact location on the device
    Info: Pin SL[2] not assigned to an exact location on the device
    Info: Pin SL[3] not assigned to an exact location on the device
    Info: Pin MH[0] not assigned to an exact location on the device
    Info: Pin MH[1] not assigned to an exact location on the device
    Info: Pin MH[2] not assigned to an exact location on the device
    Info: Pin MH[3] not assigned to an exact location on the device
    Info: Pin ML[0] not assigned to an exact location on the device
    Info: Pin ML[1] not assigned to an exact location on the device
    Info: Pin ML[2] not assigned to an exact location on the device
    Info: Pin ML[3] not assigned to an exact location on the device
    Info: Pin CLK not assigned to an exact location on the device
    Info: Pin CLR not assigned to an exact location on the device
    Info: Pin PAUSE not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "CLK" to use Global clock in PIN M20
Info: Automatically promoted some destinations of signal "cn1" to use Global clock
    Info: Destination "cn1" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "cn2" to use Global clock
    Info: Destination "cn2" may be non-global or may not use global clock
Info: Automatically promoted signal "CLR" to use Global clock in PIN M21
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished register packing: elapsed time is 00:00:00
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 25 (unused VREF, 3.30 VCCIO, 1 input, 24 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  27 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  30 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  51 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  51 pins available
        Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  29 pins available
        Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  29 pins available
        Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  52 pins available
        Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  51 pins available
        Info: I/O bank number 9 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available
        Info: I/O bank number 10 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available
        Info: I/O bank number 11 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available
        Info: I/O bank number 12 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 2.171 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X2_Y17; Fanout = 5; REG Node = 'MSL[2]~reg0'
    Info: 2: + IC(0.605 ns) + CELL(0.075 ns) = 0.680 ns; Loc. = LAB_X1_Y17; Fanout = 3; COMB Node = 'Equal0~90'
    Info: 3: + IC(0.102 ns) + CELL(0.366 ns) = 1.148 ns; Loc. = LAB_X1_Y17; Fanout = 3; COMB Node = 'MSH[0]~360'
    Info: 4: + IC(0.318 ns) + CELL(0.705 ns) = 2.171 ns; Loc. = LAB_X1_Y17; Fanout = 6; REG Node = 'MSH[0]~reg0'
    Info: Total cell delay = 1.146 ns ( 52.79 % )
    Info: Total interconnect delay = 1.025 ns ( 47.21 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%
    Info: The peak interconnect region extends from location X10_Y0 to location X20_Y9
Info: Fitter routing operations ending: elapsed time is 00:00:01
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Warning: Global route sourced by node "CLR", which is placed in Dedicated Clock "Pin_M21", begins its route with non-global routing to its global destinations. This will lead to increased delay along these routes
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 3 warnings
    Info: Allocated 202 megabytes of memory during processing
    Info: Processing ended: Tue Oct 21 15:01:37 2008
    Info: Elapsed time: 00:00:13