clk_3d.hif

来自「一个1.5分频的VHDL程序,经过编译和仿真.」· HIF 代码 · 共 58 行

Version 7.2 Build 151 09/26/2007 SJ Full Version
38
2262
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
clk_3d
# storage
db|clk_3d.(0).cnf
db|clk_3d.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
clk_3d.vhd
cc683b42cedccb4bb5e86c23b891a5d1
4
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# hierarchies {
|
}
# lmf
..|quartusii|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# complete