clk_3d.vhd

一个1.5分频的VHDL程序,经过编译和仿真.

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY clk_3d IS
  PORT(clk:IN STD_LOGIC;
       rst:IN STD_LOGIC;
      clk_out:OUT STD_LOGIC);
END clk_3d;
ARCHITECTURE m OF clk_3d IS
  SIGNAL counter1,counter2:INTEGER RANGE 0 TO 2:=0;
  SIGNAL tmp1,tmp2:STD_LOGIC:='0';
  BEGIN
     PROCESS(rst,clk)
       BEGIN
         IF(rst='0') THEN
           IF(clk'EVENT AND clk='1') THEN  
              IF counter1=2  THEN
                 counter1<=0;
               tmp1<=NOT tmp1;
             ELSIF counter1=1  THEN
               tmp1<=NOT tmp1;
               counter1<=counter1+1;
             ELSE counter1<=counter1+1;
             END IF;
           END IF;
          IF(clk'EVENT AND clk='0') THEN
              IF counter2=2 THEN
                 counter2<=0;
                 tmp2<=NOT tmp2;
              ELSIF  counter2=1 THEN
                 tmp2<=NOT tmp2;
                 counter2<=counter2+1;
              ELSE
                 counter2<=counter2+1;
              END IF;
            END IF;
          END IF;
       END PROCESS;
        clk_out<=tmp1 OR tmp2;
 END m;