clk_8.flow.rpt

来自「一个八分频的VHDL程序,经过编译和仿真.」· RPT 代码 · 共 105 行

Flow report for clk_8
Wed Oct 22 22:30:52 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Non-Default Global Settings
  5. Flow Elapsed Time
  6. Flow Log



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+---------------------------------------------------------------------+
; Flow Summary                                                        ;
+--------------------------+------------------------------------------+
; Flow Status              ; Successful - Wed Oct 22 22:30:52 2008    ;
; Quartus II Version       ; 7.2 Build 151 09/26/2007 SJ Full Version ;
; Revision Name            ; clk_8                                    ;
; Top-level Entity Name    ; clk_8                                    ;
; Family                   ; Cyclone                                  ;
; Device                   ; EP1C6Q240C6                              ;
; Timing Models            ; Final                                    ;
; Met timing requirements  ; Yes                                      ;
; Total logic elements     ; 3 / 5,980 ( < 1 % )                      ;
; Total pins               ; 2 / 185 ( 1 % )                          ;
; Total virtual pins       ; 0                                        ;
; Total memory bits        ; 0 / 92,160 ( 0 % )                       ;
; DSP block 9-bit elements ; N/A until Partition Merge                ;
; Total PLLs               ; 0 / 2 ( 0 % )                            ;
; Total DLLs               ; N/A until Partition Merge                ;
+--------------------------+------------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 10/22/2008 22:28:04 ;
; Main task         ; Compilation         ;
; Revision Name     ; clk_8               ;
+-------------------+---------------------+


+-----------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings                                                        ;
+------------------------------------+---------+---------------+-------------+------------+
; Assignment Name                    ; Value   ; Default Value ; Entity Name ; Section Id ;
+------------------------------------+---------+---------------+-------------+------------+
; PARTITION_COLOR                    ; 2147039 ; --            ; --          ; Top        ;
; PARTITION_NETLIST_TYPE             ; SOURCE  ; --            ; --          ; Top        ;
; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off     ; --            ; --          ; eda_palace ;
+------------------------------------+---------+---------------+-------------+------------+


+------------------------------------------------------------------+
; Flow Elapsed Time                                                ;
+-------------------------+--------------+-------------------------+
; Module Name             ; Elapsed Time ; Average Processors Used ;
+-------------------------+--------------+-------------------------+
; Analysis & Synthesis    ; 00:00:03     ; 1.0                     ;
; Fitter                  ; 00:00:06     ; 1.0                     ;
; Assembler               ; 00:00:02     ; 1.0                     ;
; Classic Timing Analyzer ; 00:00:01     ; 1.0                     ;
; Classic Timing Analyzer ; 00:00:01     ; 1.0                     ;
; Total                   ; 00:00:13     ; --                      ;
+-------------------------+--------------+-------------------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off clk_8 -c clk_8
quartus_fit --read_settings_files=off --write_settings_files=off clk_8 -c clk_8
quartus_asm --read_settings_files=off --write_settings_files=off clk_8 -c clk_8
quartus_tan --read_settings_files=off --write_settings_files=off clk_8 -c clk_8 --timing_analysis_only
quartus_tan --read_settings_files=on --write_settings_files=off clk_8 -c clk_8 --speed=6