prev_cmp_clk_8.tan.qmsg

一个八分频的VHDL程序,经过编译和仿真.

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clkin register register counter\[1\] clk 405.19 MHz Internal " "Info: Clock \"clkin\" Internal fmax is restricted to 405.19 MHz between source register \"counter\[1\]\" and destination register \"clk\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.234 ns 1.234 ns 2.468 ns " "Info: fmax restricted to Clock High delay (1.234 ns) plus Clock Low delay (1.234 ns) : restricted to 2.468 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.861 ns + Longest register register " "Info: + Longest register to register delay is 0.861 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter\[1\] 1 REG LC_X6_Y1_N4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y1_N4; Fanout = 2; REG Node = 'counter\[1\]'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { counter[1] } "NODE_NAME" } } { "clk_8.vhd" "" { Text "E:/QuartueII/clk_8/clk_8.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.467 ns) 0.861 ns clk 2 REG LC_X6_Y1_N9 2 " "Info: 2: + IC(0.394 ns) + CELL(0.467 ns) = 0.861 ns; Loc. = LC_X6_Y1_N9; Fanout = 2; REG Node = 'clk'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.861 ns" { counter[1] clk } "NODE_NAME" } } { "clk_8.vhd" "" { Text "E:/QuartueII/clk_8/clk_8.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.467 ns ( 54.24 % ) " "Info: Total cell delay = 0.467 ns ( 54.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.394 ns ( 45.76 % ) " "Info: Total interconnect delay = 0.394 ns ( 45.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.861 ns" { counter[1] clk } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "0.861 ns" { counter[1] {} clk {} } { 0.000ns 0.394ns } { 0.000ns 0.467ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 2.232 ns + Shortest register " "Info: + Shortest clock path from clock \"clkin\" to destination register is 2.232 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clkin 1 CLK PIN_29 3 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 3; CLK Node = 'clkin'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "clk_8.vhd" "" { Text "E:/QuartueII/clk_8/clk_8.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.555 ns) + CELL(0.547 ns) 2.232 ns clk 2 REG LC_X6_Y1_N9 2 " "Info: 2: + IC(0.555 ns) + CELL(0.547 ns) = 2.232 ns; Loc. = LC_X6_Y1_N9; Fanout = 2; REG Node = 'clk'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.102 ns" { clkin clk } "NODE_NAME" } } { "clk_8.vhd" "" { Text "E:/QuartueII/clk_8/clk_8.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 75.13 % ) " "Info: Total cell delay = 1.677 ns ( 75.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.555 ns ( 24.87 % ) " "Info: Total interconnect delay = 0.555 ns ( 24.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.232 ns" { clkin clk } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.232 ns" { clkin {} clkin~out0 {} clk {} } { 0.000ns 0.000ns 0.555ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 2.232 ns - Longest register " "Info: - Longest clock path from clock \"clkin\" to source register is 2.232 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clkin 1 CLK PIN_29 3 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 3; CLK Node = 'clkin'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "clk_8.vhd" "" { Text "E:/QuartueII/clk_8/clk_8.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.555 ns) + CELL(0.547 ns) 2.232 ns counter\[1\] 2 REG LC_X6_Y1_N4 2 " "Info: 2: + IC(0.555 ns) + CELL(0.547 ns) = 2.232 ns; Loc. = LC_X6_Y1_N4; Fanout = 2; REG Node = 'counter\[1\]'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.102 ns" { clkin counter[1] } "NODE_NAME" } } { "clk_8.vhd" "" { Text "E:/QuartueII/clk_8/clk_8.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 75.13 % ) " "Info: Total cell delay = 1.677 ns ( 75.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.555 ns ( 24.87 % ) " "Info: Total interconnect delay = 0.555 ns ( 24.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.232 ns" { clkin counter[1] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.232 ns" { clkin {} clkin~out0 {} counter[1] {} } { 0.000ns 0.000ns 0.555ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.232 ns" { clkin clk } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.232 ns" { clkin {} clkin~out0 {} clk {} } { 0.000ns 0.000ns 0.555ns } { 0.000ns 1.130ns 0.547ns } "" } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.232 ns" { clkin counter[1] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.232 ns" { clkin {} clkin~out0 {} counter[1] {} } { 0.000ns 0.000ns 0.555ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "clk_8.vhd" "" { Text "E:/QuartueII/clk_8/clk_8.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "clk_8.vhd" "" { Text "E:/QuartueII/clk_8/clk_8.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.861 ns" { counter[1] clk } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "0.861 ns" { counter[1] {} clk {} } { 0.000ns 0.394ns } { 0.000ns 0.467ns } "" } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.232 ns" { clkin clk } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.232 ns" { clkin {} clkin~out0 {} clk {} } { 0.000ns 0.000ns 0.555ns } { 0.000ns 1.130ns 0.547ns } "" } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.232 ns" { clkin counter[1] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.232 ns" { clkin {} clkin~out0 {} counter[1] {} } { 0.000ns 0.000ns 0.555ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { clk {} } {  } {  } "" } } { "clk_8.vhd" "" { Text "E:/QuartueII/clk_8/clk_8.vhd" 14 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clkin clkout clk 5.019 ns register " "Info: tco from clock \"clkin\" to destination pin \"clkout\" through register \"clk\" is 5.019 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 2.232 ns + Longest register " "Info: + Longest clock path from clock \"clkin\" to source register is 2.232 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clkin 1 CLK PIN_29 3 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 3; CLK Node = 'clkin'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "clk_8.vhd" "" { Text "E:/QuartueII/clk_8/clk_8.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.555 ns) + CELL(0.547 ns) 2.232 ns clk 2 REG LC_X6_Y1_N9 2 " "Info: 2: + IC(0.555 ns) + CELL(0.547 ns) = 2.232 ns; Loc. = LC_X6_Y1_N9; Fanout = 2; REG Node = 'clk'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.102 ns" { clkin clk } "NODE_NAME" } } { "clk_8.vhd" "" { Text "E:/QuartueII/clk_8/clk_8.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 75.13 % ) " "Info: Total cell delay = 1.677 ns ( 75.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.555 ns ( 24.87 % ) " "Info: Total interconnect delay = 0.555 ns ( 24.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.232 ns" { clkin clk } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.232 ns" { clkin {} clkin~out0 {} clk {} } { 0.000ns 0.000ns 0.555ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "clk_8.vhd" "" { Text "E:/QuartueII/clk_8/clk_8.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.614 ns + Longest register pin " "Info: + Longest register to pin delay is 2.614 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk 1 REG LC_X6_Y1_N9 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y1_N9; Fanout = 2; REG Node = 'clk'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clk_8.vhd" "" { Text "E:/QuartueII/clk_8/clk_8.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.992 ns) + CELL(1.622 ns) 2.614 ns clkout 2 PIN PIN_68 0 " "Info: 2: + IC(0.992 ns) + CELL(1.622 ns) = 2.614 ns; Loc. = PIN_68; Fanout = 0; PIN Node = 'clkout'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.614 ns" { clk clkout } "NODE_NAME" } } { "clk_8.vhd" "" { Text "E:/QuartueII/clk_8/clk_8.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.622 ns ( 62.05 % ) " "Info: Total cell delay = 1.622 ns ( 62.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.992 ns ( 37.95 % ) " "Info: Total interconnect delay = 0.992 ns ( 37.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.614 ns" { clk clkout } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.614 ns" { clk {} clkout {} } { 0.000ns 0.992ns } { 0.000ns 1.622ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.232 ns" { clkin clk } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.232 ns" { clkin {} clkin~out0 {} clk {} } { 0.000ns 0.000ns 0.555ns } { 0.000ns 1.130ns 0.547ns } "" } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.614 ns" { clk clkout } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.614 ns" { clk {} clkout {} } { 0.000ns 0.992ns } { 0.000ns 1.622ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "115 " "Info: Allocated 115 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 22 22:28:25 2008 " "Info: Processing ended: Wed Oct 22 22:28:25 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}