clk_8.tan.summary

来自「一个八分频的VHDL程序,经过编译和仿真.」· SUMMARY 代码 · 共 37 行

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 5.019 ns
From           : clk
To             : clkout
From Clock     : clkin
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'clkin'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 405.19 MHz ( period = 2.468 ns )
From           : counter[1]
To             : clk
From Clock     : clkin
To Clock       : clkin
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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