clk_8.vhd

一个八分频的VHDL程序,经过编译和仿真.

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY clk_8 IS
  PORT(clkin:IN STD_LOGIC;
       clkout:OUT STD_LOGIC);
END clk_8;
ARCHITECTURE m OF clk_8 IS
  CONSTANT N:INTEGER:=3;
  SIGNAL counter:INTEGER RANGE 0 TO N;
  SIGNAL clk:std_LOGIC;
    BEGIN
      PROCESS(clkin)
        BEGIN
          IF(clkin'EVENT AND clkin='1') THEN
             IF(counter=N) THEN
                counter<=0;
                CLK<=NOT clk;
             ELSE 
               counter<=counter+1;
             END IF;
         END IF;
       END PROCESS;
          clkout<=clk;
  END m;