📄 clk_8.tan.rpt
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Classic Timing Analyzer report for clk_8
Wed Oct 22 22:30:52 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clkin'
6. tco
7. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+------------+--------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+------------+--------+------------+----------+--------------+
; Worst-case tco ; N/A ; None ; 5.019 ns ; clk ; clkout ; clkin ; -- ; 0 ;
; Clock Setup: 'clkin' ; N/A ; None ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; counter[1] ; clk ; clkin ; clkin ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+------------+--------+------------+----------+--------------+
+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C6Q240C6 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Perform Multicorner Analysis ; Off ; ; ; ;
; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clkin ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clkin' ;
+-------+------------------------------------------------+------------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+------------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; counter[1] ; clk ; clkin ; clkin ; None ; None ; 0.861 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; counter[1] ; counter[1] ; clkin ; clkin ; None ; None ; 0.791 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; clk ; clk ; clkin ; clkin ; None ; None ; 0.780 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; counter[0] ; counter[1] ; clkin ; clkin ; None ; None ; 0.660 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; counter[0] ; clk ; clkin ; clkin ; None ; None ; 0.659 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; counter[0] ; counter[0] ; clkin ; clkin ; None ; None ; 0.655 ns ;
+-------+------------------------------------------------+------------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+----------------------------------------------------------------+
; tco ;
+-------+--------------+------------+------+--------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+------+--------+------------+
; N/A ; None ; 5.019 ns ; clk ; clkout ; clkin ;
+-------+--------------+------------+------+--------+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Wed Oct 22 22:30:51 2008
Info: Command: quartus_tan --read_settings_files=on --write_settings_files=off clk_8 -c clk_8 --speed=6
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clkin" is an undefined clock
Info: Clock "clkin" Internal fmax is restricted to 405.19 MHz between source register "counter[1]" and destination register "clk"
Info: fmax restricted to Clock High delay (1.234 ns) plus Clock Low delay (1.234 ns) : restricted to 2.468 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 0.861 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y1_N4; Fanout = 2; REG Node = 'counter[1]'
Info: 2: + IC(0.394 ns) + CELL(0.467 ns) = 0.861 ns; Loc. = LC_X6_Y1_N9; Fanout = 2; REG Node = 'clk'
Info: Total cell delay = 0.467 ns ( 54.24 % )
Info: Total interconnect delay = 0.394 ns ( 45.76 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clkin" to destination register is 2.232 ns
Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 3; CLK Node = 'clkin'
Info: 2: + IC(0.555 ns) + CELL(0.547 ns) = 2.232 ns; Loc. = LC_X6_Y1_N9; Fanout = 2; REG Node = 'clk'
Info: Total cell delay = 1.677 ns ( 75.13 % )
Info: Total interconnect delay = 0.555 ns ( 24.87 % )
Info: - Longest clock path from clock "clkin" to source register is 2.232 ns
Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 3; CLK Node = 'clkin'
Info: 2: + IC(0.555 ns) + CELL(0.547 ns) = 2.232 ns; Loc. = LC_X6_Y1_N4; Fanout = 2; REG Node = 'counter[1]'
Info: Total cell delay = 1.677 ns ( 75.13 % )
Info: Total interconnect delay = 0.555 ns ( 24.87 % )
Info: + Micro clock to output delay of source is 0.173 ns
Info: + Micro setup delay of destination is 0.029 ns
Info: tco from clock "clkin" to destination pin "clkout" through register "clk" is 5.019 ns
Info: + Longest clock path from clock "clkin" to source register is 2.232 ns
Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 3; CLK Node = 'clkin'
Info: 2: + IC(0.555 ns) + CELL(0.547 ns) = 2.232 ns; Loc. = LC_X6_Y1_N9; Fanout = 2; REG Node = 'clk'
Info: Total cell delay = 1.677 ns ( 75.13 % )
Info: Total interconnect delay = 0.555 ns ( 24.87 % )
Info: + Micro clock to output delay of source is 0.173 ns
Info: + Longest register to pin delay is 2.614 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y1_N9; Fanout = 2; REG Node = 'clk'
Info: 2: + IC(0.992 ns) + CELL(1.622 ns) = 2.614 ns; Loc. = PIN_68; Fanout = 0; PIN Node = 'clkout'
Info: Total cell delay = 1.622 ns ( 62.05 % )
Info: Total interconnect delay = 0.992 ns ( 37.95 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
Info: Allocated 120 megabytes of memory during processing
Info: Processing ended: Wed Oct 22 22:30:53 2008
Info: Elapsed time: 00:00:02
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