frequent.vhd

直流电机的VHDL源程序,经过编译和仿真.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity frequent is
    port(clk:       in std_logic;
         en:        in std_logic;
         load:      in std_logic;
         clr:       in std_logic;
         fin:       in std_logic;
         speed_dis: out std_logic_vector(15 downto 0));
end frequent;
architecture arc_fre of frequent is
    signal tmp_speed:   std_logic_vector(15 downto 0);
    signal tmp:         integer;
begin
     p1: process(fin,en,clr)
         begin
            if clr='0' then  tmp<=0;
              elsif fin'event and fin='1' then
                 if en='1' then
                    tmp<=tmp+1;
                 else tmp<=tmp;
                 end if;
             end if;
         end process p1;
      p2: process(tmp,load)
              variable a,b,c,d:integer;
          begin
             a:=tmp/1000;
             b:=(tmp-a*1000)/100;
             c:=(tmp-a*1000-b*100)/10;
             d:=tmp-a*1000-b*100-c*10;
             tmp_speed(15 downto 12)<=conv_std_logic_vector(a,4);
             tmp_speed(11 downto 8)<=conv_std_logic_vector(b,4);
             tmp_speed(7 downto 4)<=conv_std_logic_vector(c,4);
             tmp_speed(3 downto 0)<=conv_std_logic_vector(d,4);
             if load'event and load='1' then
                 speed_dis<=tmp_speed;
             end if;
          end process p2;
end arc_fre;