zhiliu_dianji.map.rpt

直流电机的VHDL源程序,经过编译和仿真.

+-----------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                              ;
+----------------------------------+-----------------+-----------------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------------+------------------------------+
; test.vhd                         ; yes             ; User VHDL File  ; E:/zhiliu_dianji/test.vhd    ;
+----------------------------------+-----------------+-----------------+------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 2     ;
;     -- Combinational with no register       ; 1     ;
;     -- Register only                        ; 0     ;
;     -- Combinational with a register        ; 1     ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 0     ;
;     -- 3 input functions                    ; 0     ;
;     -- 2 input functions                    ; 1     ;
;     -- 1 input functions                    ; 1     ;
;     -- 0 input functions                    ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 2     ;
;     -- arithmetic mode                      ; 0     ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 1     ;
; I/O pins                                    ; 4     ;
; Maximum fan-out node                        ; tmp   ;
; Maximum fan-out                             ; 4     ;
; Total fan-out                               ; 7     ;
; Average fan-out                             ; 1.17  ;
+---------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                   ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |test                      ; 2 (2)       ; 1            ; 0           ; 4    ; 0            ; 1 (1)        ; 0 (0)             ; 1 (1)            ; 0 (0)           ; 0 (0)      ; |test               ; work         ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 1     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Web Edition
    Info: Processing started: Fri Dec 21 00:56:51 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off zhiliu_dianji -c zhiliu_dianji
Info: Found 2 design units, including 1 entities, in source file d_ff.vhd
    Info: Found design unit 1: d_ff-arc_dff
    Info: Found entity 1: d_ff
Info: Found 2 design units, including 1 entities, in source file rs.vhd
    Info: Found design unit 1: rs-arc_rs
    Info: Found entity 1: rs
Info: Found 1 design units, including 1 entities, in source file qudoudong.bdf
    Info: Found entity 1: qudoudong
Info: Found 2 design units, including 1 entities, in source file PRE_F.vhd
    Info: Found design unit 1: PRE_F-ARC_PRE_F
    Info: Found entity 1: PRE_F
Info: Found 1 design units, including 1 entities, in source file zhiliu_dianji.bdf
    Info: Found entity 1: zhiliu_dianji
Info: Found 2 design units, including 1 entities, in source file dir_con.vhd
    Info: Found design unit 1: dir_con-arc_dir
    Info: Found entity 1: dir_con
Info: Found 2 design units, including 1 entities, in source file fr_pwm.vhd
    Info: Found design unit 1: fr_pwm-arc_fr
    Info: Found entity 1: fr_pwm
Warning: Can't analyze file -- file E:/zhiliu_dianji/set.vhd is missing
Info: Found 2 design units, including 1 entities, in source file frequent.vhd
    Info: Found design unit 1: frequent-arc_fre
    Info: Found entity 1: frequent
Info: Found 2 design units, including 1 entities, in source file comp.vhd
    Info: Found design unit 1: comp-arc
    Info: Found entity 1: comp
Info: Found 2 design units, including 1 entities, in source file test.vhd
    Info: Found design unit 1: test-arc
    Info: Found entity 1: test
Info: Elaborating entity "test" for the top level hierarchy
Warning: Ignored assignments for entity "comp" -- entity does not exist in design
    Warning: Assignment of entity set_global_assignment -name LL_ROOT_REGION ON -entity comp -section_id "Root Region" is ignored
    Warning: Assignment of entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity comp -section_id "Root Region" is ignored
Warning: Ignored assignments for entity "zhiliu_dianji" -- entity does not exist in design
    Warning: Assignment of entity set_global_assignment -name LL_ROOT_REGION ON -entity zhiliu_dianji -section_id "Root Region" is ignored
    Warning: Assignment of entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity zhiliu_dianji -section_id "Root Region" is ignored
Info: Implemented 6 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 3 output pins
    Info: Implemented 2 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings
    Info: Allocated 154 megabytes of memory during processing
    Info: Processing ended: Fri Dec 21 00:57:17 2007
    Info: Elapsed time: 00:00:26