alt_u_div_ste.tdf

直流电机的VHDL源程序,经过编译和仿真.

	add_sub_25 : add_sub_lec;
	add_sub_26 : add_sub_lec;
	add_sub_27 : add_sub_lec;
	add_sub_28 : add_sub_lec;
	add_sub_29 : add_sub_lec;
	add_sub_3 : add_sub_6dc;
	add_sub_30 : add_sub_lec;
	add_sub_31 : add_sub_lec;
	add_sub_4 : add_sub_7dc;
	add_sub_5 : add_sub_8dc;
	add_sub_6 : add_sub_9dc;
	add_sub_7 : add_sub_adc;
	add_sub_8 : add_sub_bdc;
	add_sub_9 : add_sub_jec;
	DenominatorIn[395..0]	: WIRE;
	DenominatorIn_tmp[395..0]	: WIRE;
	gnd_wire	: WIRE;
	nose[1055..0]	: WIRE;
	NumeratorIn[1055..0]	: WIRE;
	NumeratorIn_tmp[1055..0]	: WIRE;
	prestg[383..0]	: WIRE;
	quotient_tmp[31..0]	: WIRE;
	sel[362..0]	: WIRE;
	selnose[1055..0]	: WIRE;
	StageIn[395..0]	: WIRE;
	StageIn_tmp[395..0]	: WIRE;
	StageOut[383..0]	: WIRE;

BEGIN 
	add_sub_0.dataa[0..0] = NumeratorIn[31..31];
	add_sub_0.datab[0..0] = DenominatorIn[0..0];
	add_sub_1.dataa[] = ( StageIn[12..12], NumeratorIn[62..62]);
	add_sub_1.datab[1..0] = DenominatorIn[13..12];
	add_sub_10.dataa[] = ( StageIn[129..120], NumeratorIn[341..341]);
	add_sub_10.datab[10..0] = DenominatorIn[130..120];
	add_sub_11.dataa[] = ( StageIn[142..132], NumeratorIn[372..372]);