d_ff.vhd

直流电机的VHDL源程序,经过编译和仿真.

LIBRARY ieee;
USE ieee.std_logic_1164.all; 
LIBRARY work;
ENTITY d_ff IS 
	port(d :    IN  STD_LOGIC;
		 clk :  IN  STD_LOGIC;
		 q :    BUFFER  STD_LOGIC);
END d_ff;
ARCHITECTURE arc_dff OF d_ff IS 
BEGIN 
   process(clk)
    begin
     if (rising_edge(clk)) then
	    q<=d;
	 ELSE q<=q;
     end if;
   end process;
END;