pre_f.vhd

直流电机的VHDL源程序,经过编译和仿真.

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY PRE_F IS
   PORT
    ( pre:   IN STD_LOGIC_VECTOR(3 DOWNTO 0);
      f_pre: OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
END PRE_F;

ARCHITECTURE ARC_PRE_F OF PRE_F IS
   SIGNAL f_tmp: STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
   P1:PROCESS(pre)
      BEGIN
         IF pre(3)'EVENT AND pre(3)='1' THEN
            IF f_tmp(15 DOWNTO 12)="1001" THEN
               f_tmp(15 DOWNTO 12)<="0000";
            ELSE f_tmp(15 DOWNTO 12)<=f_tmp(15 DOWNTO 12)+1;
            END IF;
         END IF;

         IF pre(2)'EVENT AND pre(2)='1' THEN
            IF f_tmp(11 DOWNTO 8)="1001" THEN
               f_tmp(11 DOWNTO 8)<="0000";
            ELSE f_tmp(11 DOWNTO 8)<=f_tmp(11 DOWNTO 8)+1;
            END IF;
         END IF;

         IF pre(1)'EVENT AND pre(1)='1' THEN
            IF f_tmp(7 DOWNTO 4)="1001" THEN
               f_tmp(7 DOWNTO 4)<="0000";
            ELSE f_tmp(7 DOWNTO 4)<=f_tmp(7 DOWNTO 4)+1;
            END IF;
         END IF;

         IF pre(0)'EVENT AND pre(0)='1' THEN
            IF f_tmp(3 DOWNTO 0)="1001" THEN
               f_tmp(3 DOWNTO 0)<="0000";
            ELSE f_tmp(3 DOWNTO 0)<=f_tmp(3 DOWNTO 0)+1;
            END IF;
         END IF;
            f_pre<=f_tmp;
      END PROCESS P1;
END ARC_PRE_F;