test.vhd

直流电机的VHDL源程序,经过编译和仿真.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity test is
    port(clk:    in std_logic;
         en:     out std_logic;
         load:   out std_logic;
         clr:    out std_logic);
end test;
architecture arc of test is
    signal tmp:std_logic;
begin
   p1:process(clk)
	  begin
		if clk'event and clk='1' then
		   tmp<=not tmp;
		end if;
      end process p1;
   p2:process(clk,tmp)
	  begin
		if clk='0' and tmp='0' then
		   clr<='0';
		else clr<='1';
		end if;	
      end process p2;
   load<=not tmp;
   en<=tmp;
end arc;