fr_pwm.vhd

直流电机的VHDL源程序,经过编译和仿真.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fr_pwm is
   port(clk:   in std_logic;
        fr_p:  out std_logic_vector(9 downto 0));
end fr_pwm;
architecture arc_fr of fr_pwm is
   signal tmp:  integer range 0 to 1000;
begin
   process(clk)
   begin 
      if clk'event and clk='1' then
         if tmp=1000 then
            tmp<=0;
          else 
            tmp<=tmp+1;
          end if;
       end if;
    end process;
      fr_p<=conv_std_logic_vector(tmp,10);
end arc_fr;