rs.vhd

直流电机的VHDL源程序,经过编译和仿真.

LIBRARY ieee;
USE ieee.std_logic_1164.all; 
LIBRARY work;
ENTITY rs IS 
	port(s,r:    IN  STD_LOGIC;
		 q :     buffer  STD_LOGIC);
END rs;
ARCHITECTURE arc_rs OF rs IS 
BEGIN 
   process(s,r)
    begin
      if s='0' and r='1' then
         q<='0';
      elsif s='1' and r='0' then
         q<='1';
      else
         q<=q;
      end if;
   end process;
END;