comp.vhd

直流电机的VHDL源程序,经过编译和仿真.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity comp is
    port( d:in std_logic_vector(9 downto 0);
          f_pwm:in std_logic_vector(9 downto 0);
          w_pwm:out std_logic);
end comp;
architecture arc of comp is
begin
   process(d,f_pwm)
   begin
      if f_pwm<=d then
         w_pwm<='1';
      else
         w_pwm<='0';
      end if;
    end process;
end arc;