dir_con.vhd.bak

直流电机的VHDL源程序,经过编译和仿真.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dir_con is
    port(w_pwm:   in std_logic;
         s:       in std_logic;
         forward: out std_logic;
         back:    out std_logic);
end dir_con;
architecture arc_dir of dir_con is
begin 
    process(s,w_pwm)
    begin
       case s is
         when '0'   =>forward<=w_pwm; back<='0';
         when '1'   =>forward<='0';   back<=w_pwm;
         when others=>forward<=w_pwm; back<='0';
       end case;
    end process;
end arc_dir;