📄 zhiliu_dianji.tan.rpt
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Classic Timing Analyzer report for zhiliu_dianji
Fri Dec 21 00:58:16 2007
Quartus II Version 7.2 Build 151 09/26/2007 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tco
7. tpd
8. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+------+-----+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+------+-----+------------+----------+--------------+
; Worst-case tco ; N/A ; None ; 5.902 ns ; tmp ; clr ; clk ; -- ; 0 ;
; Worst-case tpd ; N/A ; None ; 7.406 ns ; clk ; clr ; -- ; -- ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; tmp ; tmp ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+------+-----+------------+----------+--------------+
+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C6Q240C6 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Perform Multicorner Analysis ; Off ; ; ; ;
; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+------+-----+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+------+-----+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; tmp ; tmp ; clk ; clk ; None ; None ; 0.645 ns ;
+-------+------------------------------------------------+------+-----+------------+----------+-----------------------------+---------------------------+-------------------------+
+--------------------------------------------------------------+
; tco ;
+-------+--------------+------------+------+------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+------+------+------------+
; N/A ; None ; 5.902 ns ; tmp ; clr ; clk ;
; N/A ; None ; 4.997 ns ; tmp ; load ; clk ;
; N/A ; None ; 4.997 ns ; tmp ; en ; clk ;
+-------+--------------+------------+------+------+------------+
+----------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+-----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+-----+
; N/A ; None ; 7.406 ns ; clk ; clr ;
+-------+-------------------+-----------------+------+-----+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 7.2 Build 151 09/26/2007 SJ Web Edition
Info: Processing started: Fri Dec 21 00:58:12 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off zhiliu_dianji -c zhiliu_dianji --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 405.19 MHz between source register "tmp" and destination register "tmp"
Info: fmax restricted to Clock High delay (1.234 ns) plus Clock Low delay (1.234 ns) : restricted to 2.468 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 0.645 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y17_N3; Fanout = 4; REG Node = 'tmp'
Info: 2: + IC(0.407 ns) + CELL(0.238 ns) = 0.645 ns; Loc. = LC_X1_Y17_N3; Fanout = 4; REG Node = 'tmp'
Info: Total cell delay = 0.238 ns ( 36.90 % )
Info: Total interconnect delay = 0.407 ns ( 63.10 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clk" to destination register is 2.305 ns
Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_11; Fanout = 2; CLK Node = 'clk'
Info: 2: + IC(0.628 ns) + CELL(0.547 ns) = 2.305 ns; Loc. = LC_X1_Y17_N3; Fanout = 4; REG Node = 'tmp'
Info: Total cell delay = 1.677 ns ( 72.75 % )
Info: Total interconnect delay = 0.628 ns ( 27.25 % )
Info: - Longest clock path from clock "clk" to source register is 2.305 ns
Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_11; Fanout = 2; CLK Node = 'clk'
Info: 2: + IC(0.628 ns) + CELL(0.547 ns) = 2.305 ns; Loc. = LC_X1_Y17_N3; Fanout = 4; REG Node = 'tmp'
Info: Total cell delay = 1.677 ns ( 72.75 % )
Info: Total interconnect delay = 0.628 ns ( 27.25 % )
Info: + Micro clock to output delay of source is 0.173 ns
Info: + Micro setup delay of destination is 0.029 ns
Info: tco from clock "clk" to destination pin "clr" through register "tmp" is 5.902 ns
Info: + Longest clock path from clock "clk" to source register is 2.305 ns
Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_11; Fanout = 2; CLK Node = 'clk'
Info: 2: + IC(0.628 ns) + CELL(0.547 ns) = 2.305 ns; Loc. = LC_X1_Y17_N3; Fanout = 4; REG Node = 'tmp'
Info: Total cell delay = 1.677 ns ( 72.75 % )
Info: Total interconnect delay = 0.628 ns ( 27.25 % )
Info: + Micro clock to output delay of source is 0.173 ns
Info: + Longest register to pin delay is 3.424 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y17_N3; Fanout = 4; REG Node = 'tmp'
Info: 2: + IC(0.394 ns) + CELL(0.340 ns) = 0.734 ns; Loc. = LC_X1_Y17_N4; Fanout = 1; COMB Node = 'p2~0'
Info: 3: + IC(1.068 ns) + CELL(1.622 ns) = 3.424 ns; Loc. = PIN_240; Fanout = 0; PIN Node = 'clr'
Info: Total cell delay = 1.962 ns ( 57.30 % )
Info: Total interconnect delay = 1.462 ns ( 42.70 % )
Info: Longest tpd from source pin "clk" to destination pin "clr" is 7.406 ns
Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_11; Fanout = 2; CLK Node = 'clk'
Info: 2: + IC(3.498 ns) + CELL(0.088 ns) = 4.716 ns; Loc. = LC_X1_Y17_N4; Fanout = 1; COMB Node = 'p2~0'
Info: 3: + IC(1.068 ns) + CELL(1.622 ns) = 7.406 ns; Loc. = PIN_240; Fanout = 0; PIN Node = 'clr'
Info: Total cell delay = 2.840 ns ( 38.35 % )
Info: Total interconnect delay = 4.566 ns ( 61.65 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
Info: Allocated 112 megabytes of memory during processing
Info: Processing ended: Fri Dec 21 00:58:16 2007
Info: Elapsed time: 00:00:04
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