pxi_dsp_da.tan.rpt

双口RAM与PXI总线接口设计

; Worst-case tsu               ; N/A   ; None          ; 5.906 ns                         ; DSP_AB[5]                                                                                                                                                ; ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~porta_address_reg5                                            ; --         ; Yx2       ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 11.535 ns                        ; ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|q_b[7]                           ; CH365_DB[7]                                                                                                                                             ; R/W        ; --        ; 0            ;
; Worst-case tpd               ; N/A   ; None          ; 4.031 ns                         ; DSP_CLOCK                                                                                                                                                ; DA7744_CS                                                                                                                                               ; --         ; --        ; 0            ;
; Worst-case th                ; N/A   ; None          ; 0.448 ns                         ; CH365[4]                                                                                                                                                 ; ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|ram_block1a5~portb_address_reg4 ; --         ; R/W       ; 0            ;
; Clock Setup: 'R/W'           ; N/A   ; None          ; 219.30 MHz ( period = 4.560 ns ) ; ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|q_b[7]                           ; ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|ram_block1a7~porta_datain_reg0  ; R/W        ; R/W       ; 0            ;
; Clock Setup: 'MEMR'          ; N/A   ; None          ; 255.95 MHz ( period = 3.907 ns ) ; ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component1|altsyncram:ram_block|altsyncram_5bp1:auto_generated|ram_block1a1~portb_address_reg10 ; ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component1|altsyncram:ram_block|altsyncram_5bp1:auto_generated|q_b[0]                          ; MEMR       ; MEMR      ; 0            ;
; Clock Setup: 'DSP_CLOCK'     ; N/A   ; None          ; 255.95 MHz ( period = 3.907 ns ) ; ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a1~portb_address_reg10                                             ; ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|q_b[0]                                                                      ; DSP_CLOCK  ; DSP_CLOCK ; 0            ;
; Clock Setup: 'Yx1'           ; N/A   ; None          ; 256.02 MHz ( period = 3.906 ns ) ; ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component1|altsyncram:ram_block|altsyncram_5bp1:auto_generated|ram_block1a1~porta_datain_reg1   ; ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component1|altsyncram:ram_block|altsyncram_5bp1:auto_generated|ram_block1a1~porta_memory_reg1  ; Yx1        ; Yx1       ; 0            ;
; Clock Setup: 'MEMW'          ; N/A   ; None          ; 256.02 MHz ( period = 3.906 ns ) ; ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component1|altsyncram:ram_block|altsyncram_5bp1:auto_generated|ram_block1a1~porta_datain_reg1   ; ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component1|altsyncram:ram_block|altsyncram_5bp1:auto_generated|ram_block1a1~porta_memory_reg1  ; MEMW       ; MEMW      ; 0            ;
; Clock Setup: 'A13'           ; N/A   ; None          ; 256.02 MHz ( period = 3.906 ns ) ; ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component1|altsyncram:ram_block|altsyncram_5bp1:auto_generated|ram_block1a1~porta_datain_reg1   ; ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component1|altsyncram:ram_block|altsyncram_5bp1:auto_generated|ram_block1a1~porta_memory_reg1  ; A13        ; A13       ; 0            ;
; Clock Setup: 'Yx2'           ; N/A   ; None          ; 256.02 MHz ( period = 3.906 ns ) ; ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a1~porta_datain_reg1                                               ; ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a1~porta_memory_reg1                                              ; Yx2        ; Yx2       ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;                                                                                                                                                          ;                                                                                                                                                         ;            ;           ; 0            ;
+------------------------------+-------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+------------+-----------+--------------+


+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                      ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                         ; Setting            ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                    ; EP1C6Q240C6        ;      ;    ;             ;
; Timing Models                                                  ; Final              ;      ;    ;             ;
; Default hold multicycle                                        ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                      ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                         ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                 ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                               ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                          ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                        ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                               ; Off                ;      ;    ;             ;
; Enable Clock Latency                                           ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node          ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                          ; 10                 ;      ;    ;             ;
; Number of paths to report                                      ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                   ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                         ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                     ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                   ; Off                ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis ; Off                ;      ;    ;             ;
+----------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; DSP_CLOCK       ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; Yx2             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; MEMR            ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;