display.vhd

来自「数字显示当前的小时、分钟、秒； 2、可以预置为12小时计时显示和24小时计时显」· VHDL 代码 · 共 24 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DISPLAY IS
   PORT(DATA:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
        Q_OUT:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END DISPLAY;
ARCHITECTURE DISP_ARE OF DISPLAY IS
BEGIN
     PROCESS(DATA)
       BEGIN
CASE DATA IS
    WHEN"0000" =>Q_OUT<="0111111";
    WHEN"0001" =>Q_OUT<="0000110";
    WHEN"0010" =>Q_OUT<="1011011";
    WHEN"0011" =>Q_OUT<="1001111";
    WHEN"0100" =>Q_OUT<="1100110";
    WHEN"0101" =>Q_OUT<="1101101";
    WHEN"0110" =>Q_OUT<="1111101";
    WHEN"0111" =>Q_OUT<="0100111";
    WHEN"1000" =>Q_OUT<="1111111";
    WHEN OTHERS =>Q_OUT<="1101111";
END CASE;
  END PROCESS;
END DISP_ARE;