prev_cmp_total.qmsg

数字显示当前的小时、分钟、秒； 2、可以预置为12小时计时显示和24小时计时显示； 3、一个调节键

{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "MIN_COUT CLK_CHOOSE.vhd(29) " "Warning (10492): VHDL Process Statement warning at CLK_CHOOSE.vhd(29): signal \"MIN_COUT\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "CLK_CHOOSE.vhd" "" { Text "J:/ALL/CLK_CHOOSE.vhd" 29 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SECOND SECOND:inst1 " "Info: Elaborating entity \"SECOND\" for hierarchy \"SECOND:inst1\"" {  } { { "TOTAL.bdf" "inst1" { Schematic "J:/ALL/TOTAL.bdf" { { 0 328 496 96 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "MINUTE MINUTE:inst " "Info: Elaborating entity \"MINUTE\" for hierarchy \"MINUTE:inst\"" {  } { { "TOTAL.bdf" "inst" { Schematic "J:/ALL/TOTAL.bdf" { { 120 328 472 216 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "RESET MINUTE.vhd(14) " "Warning (10492): VHDL Process Statement warning at MINUTE.vhd(14): signal \"RESET\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "MINUTE.vhd" "" { Text "J:/ALL/MINUTE.vhd" 14 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DISPLAY DISPLAY:inst4 " "Info: Elaborating entity \"DISPLAY\" for hierarchy \"DISPLAY:inst4\"" {  } { { "TOTAL.bdf" "inst4" { Schematic "J:/ALL/TOTAL.bdf" { { 72 768 936 168 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SELTIME SELTIME:inst5 " "Info: Elaborating entity \"SELTIME\" for hierarchy \"SELTIME:inst5\"" {  } { { "TOTAL.bdf" "inst5" { Schematic "J:/ALL/TOTAL.bdf" { { 72 560 728 232 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "COUNT seltime.vhd(25) " "Warning (10492): VHDL Process Statement warning at seltime.vhd(25): signal \"COUNT\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "seltime.vhd" "" { Text "J:/ALL/seltime.vhd" 25 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "SEC0 seltime.vhd(26) " "Warning (10492): VHDL Process Statement warning at seltime.vhd(26): signal \"SEC0\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "seltime.vhd" "" { Text "J:/ALL/seltime.vhd" 26 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "SEC1 seltime.vhd(27) " "Warning (10492): VHDL Process Statement warning at seltime.vhd(27): signal \"SEC1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "seltime.vhd" "" { Text "J:/ALL/seltime.vhd" 27 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "MIN0 seltime.vhd(28) " "Warning (10492): VHDL Process Statement warning at seltime.vhd(28): signal \"MIN0\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "seltime.vhd" "" { Text "J:/ALL/seltime.vhd" 28 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "MIN1 seltime.vhd(29) " "Warning (10492): VHDL Process Statement warning at seltime.vhd(29): signal \"MIN1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "seltime.vhd" "" { Text "J:/ALL/seltime.vhd" 29 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "H0 seltime.vhd(30) " "Warning (10492): VHDL Process Statement warning at seltime.vhd(30): signal \"H0\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "seltime.vhd" "" { Text "J:/ALL/seltime.vhd" 30 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "H1 seltime.vhd(31) " "Warning (10492): VHDL Process Statement warning at seltime.vhd(31): signal \"H1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "seltime.vhd" "" { Text "J:/ALL/seltime.vhd" 31 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 0}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "2 " "Info: Inferred 2 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "HOUR:inst3\|Add1 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"HOUR:inst3\|Add1\"" {  } { { "d:/program files/quartusii8.0/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "Add1" { Text "d:/program files/quartusii8.0/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "HOUR:inst3\|Add0 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"HOUR:inst3\|Add0\"" {  } { { "d:/program files/quartusii8.0/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "Add0" { Text "d:/program files/quartusii8.0/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0 0}