total.sim.talkback.xml

数字显示当前的小时、分钟、秒； 2、可以预置为12小时计时显示和24小时计时显示； 3、一个调节键

<!--
This XML file (created on Wed Oct 29 20:38:14 2008) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to www.altera.com/products/software/download/dnl-download_license.html
-->
<talkback>
<ver>5.1</ver>
<schema>quartus_version_5.1_build_176.xsd</schema><license>
	<nic_id>001e9006b92f</nic_id>
	<cdrive_id>c8766079</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>5.1</version>
	<build>Build 176</build>
	<binary_type>32</binary_type>
	<module>quartus_sim.exe</module>
	<edition>Web Edition</edition>
	<eval>Eval</eval>
	<compilation_end_time>Wed Oct 29 20:38:15 2008</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>2</proc_count>
		<cpu_freq units="MHz">2099</cpu_freq>
	</cpu>
	<ram units="MB">768</ram>
</machine>
<top_file>J:/ALL/TOTAL</top_file>
<mep_data>
	<command_line>quartus_sim --read_settings_files=on --write_settings_files=off TOTAL -c TOTAL</command_line>
</mep_data>
<messages>
	<info>Info: Quartus II Simulator was successful. 0 errors, 0 warnings</info>
	<info>Info: Elapsed time: 00:00:01</info>
	<info>Info: Processing ended: Wed Oct 29 20:38:14 2008</info>
	<info>Info: Number of transitions in simulation is 199</info>
	<info>Info: Simulation coverage is       1.96 %</info>
</messages>
<simulator_settings>
	<row>
		<option>Simulation mode</option>
		<setting>Timing</setting>
		<default_value>Timing</default_value>
	</row>
	<row>
		<option>Start time</option>
		<setting units="ns">0</setting>
		<default_value units="ns">0</default_value>
	</row>
	<row>
		<option>Add pins automatically to simulation output waveforms</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Check outputs</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Report simulation coverage</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Detect setup and hold time violations</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Detect glitches</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Automatically save/load simulation netlist</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Disable timing delays in Timing Simulation</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Generate Signal Activity File</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Group bus channels in simulation results</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Preserve fewer signal transitions to reduce memory requirements</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Overwrite Waveform Inputs With Simulation Outputs</option>
		<setting>Off</setting>
	</row>
</simulator_settings>
<simulator_summary>
	<simulation_start_time>0 ps</simulation_start_time>
	<simulation_end_time>1.0 us</simulation_end_time>
	<simulation_netlist_size>56 nodes</simulation_netlist_size>
	<simulation_coverage>      1.96 %</simulation_coverage>
	<total_number_of_transitions>199</total_number_of_transitions>
	<family>Stratix</family>
	<device>EP1S10F484C5</device>
</simulator_summary>
<compile_id>989CA610</compile_id>
</talkback>