📄 freedev_cycloneii_50.fit.qmsg
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{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0}
{ "Warning" "WDAT_PRELIMINARY_TIMING" "EP2C35F484C8 " "Warning: Timing characteristics of device EP2C35F484C8 are preliminary" { } { } 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "50 " "Warning: Found 50 output pins without output pin load capacitance assignment" { { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "FCS 0 " "Warning: Pin \"FCS\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "FRD 0 " "Warning: Pin \"FRD\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "FWR 0 " "Warning: Pin \"FWR\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_CE 0 " "Warning: Pin \"SRAM_CE\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_OE 0 " "Warning: Pin \"SRAM_OE\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_WE 0 " "Warning: Pin \"SRAM_WE\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "NET_AEN 0 " "Warning: Pin \"NET_AEN\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "NET_IOR 0 " "Warning: Pin \"NET_IOR\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "NET_IOW 0 " "Warning: Pin \"NET_IOW\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[24\] 0 " "Warning: Pin \"A\[24\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[23\] 0 " "Warning: Pin \"A\[23\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[22\] 0 " "Warning: Pin \"A\[22\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[21\] 0 " "Warning: Pin \"A\[21\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[20\] 0 " "Warning: Pin \"A\[20\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[19\] 0 " "Warning: Pin \"A\[19\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[18\] 0 " "Warning: Pin \"A\[18\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[17\] 0 " "Warning: Pin \"A\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[16\] 0 " "Warning: Pin \"A\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[15\] 0 " "Warning: Pin \"A\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[14\] 0 " "Warning: Pin \"A\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[13\] 0 " "Warning: Pin \"A\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[12\] 0 " "Warning: Pin \"A\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[11\] 0 " "Warning: Pin \"A\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[10\] 0 " "Warning: Pin \"A\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[9\] 0 " "Warning: Pin \"A\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[8\] 0 " "Warning: Pin \"A\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[7\] 0 " "Warning: Pin \"A\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[6\] 0 " "Warning: Pin \"A\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[5\] 0 " "Warning: Pin \"A\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[4\] 0 " "Warning: Pin \"A\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[3\] 0 " "Warning: Pin \"A\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[2\] 0 " "Warning: Pin \"A\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[1\] 0 " "Warning: Pin \"A\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[0\] 0 " "Warning: Pin \"A\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "D\[15\] 0 " "Warning: Pin \"D\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "D\[14\] 0 " "Warning: Pin \"D\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "D\[13\] 0 " "Warning: Pin \"D\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "D\[12\] 0 " "Warning: Pin \"D\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "D\[11\] 0 " "Warning: Pin \"D\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "D\[10\] 0 " "Warning: Pin \"D\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "D\[9\] 0 " "Warning: Pin \"D\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "D\[8\] 0 " "Warning: Pin \"D\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "D\[7\] 0 " "Warning: Pin \"D\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "D\[6\] 0 " "Warning: Pin \"D\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "D\[5\] 0 " "Warning: Pin \"D\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "D\[4\] 0 " "Warning: Pin \"D\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "D\[3\] 0 " "Warning: Pin \"D\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "D\[2\] 0 " "Warning: Pin \"D\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "D\[1\] 0 " "Warning: Pin \"D\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "D\[0\] 0 " "Warning: Pin \"D\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} } { } 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "50 " "Warning: Found 50 output pins without output pin load capacitance assignment" { { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "FCS 0 " "Warning: Pin \"FCS\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "FRD 0 " "Warning: Pin \"FRD\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "FWR 0 " "Warning: Pin \"FWR\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_CE 0 " "Warning: Pin \"SRAM_CE\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_OE 0 " "Warning: Pin \"SRAM_OE\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_WE 0 " "Warning: Pin \"SRAM_WE\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "NET_AEN 0 " "Warning: Pin \"NET_AEN\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "NET_IOR 0 " "Warning: Pin \"NET_IOR\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "NET_IOW 0 " "Warning: Pin \"NET_IOW\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[24\] 0 " "Warning: Pin \"A\[24\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[23\] 0 " "Warning: Pin \"A\[23\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[22\] 0 " "Warning: Pin \"A\[22\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[21\] 0 " "Warning: Pin \"A\[21\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[20\] 0 " "Warning: Pin \"A\[20\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[19\] 0 " "Warning: Pin \"A\[19\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[18\] 0 " "Warning: Pin \"A\[18\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[17\] 0 " "Warning: Pin \"A\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[16\] 0 " "Warning: Pin \"A\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[15\] 0 " "Warning: Pin \"A\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[14\] 0 " "Warning: Pin \"A\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[13\] 0 " "Warning: Pin \"A\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[12\] 0 " "Warning: Pin \"A\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[11\] 0 " "Warning: Pin \"A\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[10\] 0 " "Warning: Pin \"A\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[9\] 0 " "Warning: Pin \"A\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[8\] 0 " "Warning: Pin \"A\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[7\] 0 " "Warning: Pin \"A\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[6\] 0 " "Warning: Pin \"A\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[5\] 0 " "Warning: Pin \"A\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[4\] 0 " "Warning: Pin \"A\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[3\] 0 " "Warning: Pin \"A\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[2\] 0 " "Warning: Pin \"A\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[1\] 0 " "Warning: Pin \"A\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "A\[0\] 0 " "Warning: Pin \"A\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "D\[15\] 0 " "Warning: Pin \"D\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "D\[14\] 0 " "Warning: Pin \"D\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "D\[13\] 0 " "Warning: Pin \"D\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "D\[12\] 0 " "Warning: Pin \"D\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "D\[11\] 0 " "Warning: Pin \"D\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "D\[10\] 0 " "Warning: Pin \"D\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "D\[9\] 0 " "Warning: Pin \"D\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "D\[8\] 0 " "Warning: Pin \"D\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "D\[7\] 0 " "Warning: Pin \"D\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "D\[6\] 0 " "Warning: Pin \"D\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "D\[5\] 0 " "Warning: Pin \"D\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "D\[4\] 0 " "Warning: Pin \"D\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "D\[3\] 0 " "Warning: Pin \"D\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "D\[2\] 0 " "Warning: Pin \"D\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "D\[1\] 0 " "Warning: Pin \"D\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "D\[0\] 0 " "Warning: Pin \"D\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0} } { } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "freedev_cycloneII_50:inst\|freedev_cycloneII_50_reset_clk_domain_synch_module:freedev_cycloneII_50_reset_clk_domain_synch\|data_out~clkctrl " "Info: Node freedev_cycloneII_50:inst\|freedev_cycloneII_50_reset_clk_domain_synch_module:freedev_cycloneII_50_reset_clk_domain_synch\|data_out~clkctrl uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear freedev_cycloneII_50:inst\|cpu_0:the_cpu_0\|W_valid " "Info: Port clear -- assigned as a global for destination node freedev_cycloneII_50:inst\|cpu_0:the_cpu_0\|W_valid -- routed using non-global resources" { } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "" { freedev_cycloneII_50:inst|cpu_0:the_cpu_0|W_valid } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "freedev_cycloneII_50:inst\|cpu_0:the_cpu_0\|W_valid" } } } } { "cpu_0.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0.v" 600 -1 0 } } { "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.fld" "" { Floorplan "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.fld" "" "" { freedev_cycloneII_50:inst|cpu_0:the_cpu_0|W_valid } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear freedev_cycloneII_50:inst\|cpu_0:the_cpu_0\|R_dst_regnum\[3\] " "Info: Port clear -- assigned as a global for destination node freedev_cycloneII_50:inst\|cpu_0:the_cpu_0\|R_dst_regnum\[3\] -- routed using non-global resources" { } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "" { freedev_cycloneII_50:inst|cpu_0:the_cpu_0|R_dst_regnum[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "freedev_cycloneII_50:inst\|cpu_0:the_cpu_0\|R_dst_regnum\[3\]" } } } } { "cpu_0.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0.v" 565 -1 0 } } { "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.fld" "" { Floorplan "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.fld" "" "" { freedev_cycloneII_50:inst|cpu_0:the_cpu_0|R_dst_regnum[3] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear freedev_cycloneII_50:inst\|cpu_0:the_cpu_0\|R_dst_regnum\[4\] " "Info: Port clear -- assigned as a global for destination node freedev_cycloneII_50:inst\|cpu_0:the_cpu_0\|R_dst_regnum\[4\] -- routed using non-global resources" { } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "" { freedev_cycloneII_50:inst|cpu_0:the_cpu_0|R_dst_regnum[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "freedev_cycloneII_50:inst\|cpu_0:the_cpu_0\|R_dst_regnum\[4\]" } } } } { "cpu_0.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0.v" 565 -1 0 } } { "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.fld" "" { Floorplan "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.fld" "" "" { freedev_cycloneII_50:inst|cpu_0:the_cpu_0|R_dst_regnum[4] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear freedev_cycloneII_50:inst\|cpu_0:the_cpu_0\|R_dst_regnum\[2\] " "Info: Port clear -- assigned as a global for destination node freedev_cycloneII_50:inst\|cpu_0:the_cpu_0\|R_dst_regnum\[2\] -- routed using non-global resources" { } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "" { freedev_cycloneII_50:inst|cpu_0:the_cpu_0|R_dst_regnum[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "freedev_cycloneII_50:inst\|cpu_0:the_cpu_0\|R_dst_regnum\[2\]" } } } } { "cpu_0.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0.v" 565 -1 0 } } { "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.fld" "" { Floorplan "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.fld" "" "" { freedev_cycloneII_50:inst|cpu_0:the_cpu_0|R_dst_regnum[2] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear freedev_cycloneII_50:inst\|cpu_0:the_cpu_0\|R_dst_regnum\[1\] " "Info: Port clear -- assigned as a global for destination node freedev_cycloneII_50:inst\|cpu_0:the_cpu_0\|R_dst_regnum\[1\] -- routed using non-global resources" { } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "" { freedev_cycloneII_50:inst|cpu_0:the_cpu_0|R_dst_regnum[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "freedev_cycloneII_50:inst\|cpu_0:the_cpu_0\|R_dst_regnum\[1\]" } } } } { "cpu_0.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0.v" 565 -1 0 } } { "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.fld" "" { Floorplan "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.fld" "" "" { freedev_cycloneII_50:inst|cpu_0:the_cpu_0|R_dst_regnum[1] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear freedev_cycloneII_50:inst\|cpu_0:the_cpu_0\|R_dst_regnum\[0\] " "Info: Port clear -- assigned as a global for destination node freedev_cycloneII_50:inst\|cpu_0:the_cpu_0\|R_dst_regnum\[0\] -- routed using non-global resources" { } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "" { freedev_cycloneII_50:inst|cpu_0:the_cpu_0|R_dst_regnum[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "freedev_cycloneII_50:inst\|cpu_0:the_cpu_0\|R_dst_regnum\[0\]" } } } } { "cpu_0.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0.v" 565 -1 0 } } { "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.fld" "" { Floorplan "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.fld" "" "" { freedev_cycloneII_50:inst|cpu_0:the_cpu_0|R_dst_regnum[0] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear freedev_cycloneII_50:inst\|cpu_0:the_cpu_0\|R_wr_dst_reg " "Info: Port clear -- assigned as a global for destination node freedev_cycloneII_50:inst\|cpu_0:the_cpu_0\|R_wr_dst_reg -- routed using non-global resources" { } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "" { freedev_cycloneII_50:inst|cpu_0:the_cpu_0|R_wr_dst_reg } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "freedev_cycloneII_50:inst\|cpu_0:the_cpu_0\|R_wr_dst_reg" } } } } { "cpu_0.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0.v" 579 -1 0 } } { "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.fld" "" { Floorplan "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.fld" "" "" { freedev_cycloneII_50:inst|cpu_0:the_cpu_0|R_wr_dst_reg } "NODE_NAME" } } } 0} } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "" { freedev_cycloneII_50:inst|freedev_cycloneII_50_reset_clk_domain_synch_module:freedev_cycloneII_50_reset_clk_domain_synch|data_out~clkctrl } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "freedev_cycloneII_50:inst\|freedev_cycloneII_50_reset_clk_domain_synch_module:freedev_cycloneII_50_reset_clk_domain_synch\|data_out~clkctrl" } } } } { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 3193 -1 0 } } { "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.fld" "" { Floorplan "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.fld" "" "" { freedev_cycloneII_50:inst|freedev_cycloneII_50_reset_clk_domain_synch_module:freedev_cycloneII_50_reset_clk_domain_synch|data_out~clkctrl } "NODE_NAME" } } } 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_hub:sld_hub_inst\|CLEAR_SIGNAL~0clkctrl " "Info: Node sld_hub:sld_hub_inst\|CLEAR_SIGNAL~0clkctrl uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear freedev_cycloneII_50:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|count\[9\] " "Info: Port clear -- assigned as a global for destination node freedev_cycloneII_50:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uar⌨️ 快捷键说明
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