freedev_cycloneii_50.fit.qmsg

verilog 代码

{ "Info" "IFITAPI_FITAPI_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.651 ns register register " "Info: Estimated most critical path is register to register delay of 3.651 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[0\] 1 REG LAB_X10_Y19 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X10_Y19; Fanout = 4; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[0\]'" {  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] } "NODE_NAME" } "" } } { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.940 ns) + CELL(0.664 ns) 1.604 ns freedev_cycloneII_50:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|always0~53 2 COMB LAB_X10_Y18 4 " "Info: 2: + IC(0.940 ns) + CELL(0.664 ns) = 1.604 ns; Loc. = LAB_X10_Y18; Fanout = 4; COMB Node = 'freedev_cycloneII_50:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|always0~53'" {  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "1.604 ns" { sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|always0~53 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.180 ns) + CELL(0.636 ns) 2.420 ns freedev_cycloneII_50:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate~0 3 COMB LAB_X10_Y18 1 " "Info: 3: + IC(0.180 ns) + CELL(0.636 ns) = 2.420 ns; Loc. = LAB_X10_Y18; Fanout = 1; COMB Node = 'freedev_cycloneII_50:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate~0'" {  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "0.816 ns" { freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|always0~53 freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate~0 } "NODE_NAME" } "" } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_jtag_atlantic.v" 203 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.359 ns) + CELL(0.872 ns) 3.651 ns freedev_cycloneII_50:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate 4 REG LAB_X10_Y18 2 " "Info: 4: + IC(0.359 ns) + CELL(0.872 ns) = 3.651 ns; Loc. = LAB_X10_Y18; Fanout = 2; REG Node = 'freedev_cycloneII_50:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate'" {  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "1.231 ns" { freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate~0 freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } "NODE_NAME" } "" } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_jtag_atlantic.v" 203 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.172 ns 59.49 % " "Info: Total cell delay = 2.172 ns ( 59.49 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.479 ns 40.51 % " "Info: Total interconnect delay = 1.479 ns ( 40.51 % )" {  } {  } 0}  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "3.651 ns" { sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|always0~53 freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate~0 freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:06 " "Info: Fitter placement operations ending: elapsed time is 00:00:06" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "3 26 " "Info: Average interconnect usage is 3% of the available device resources. Peak interconnect usage is 26%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:05 " "Info: Fitter routing operations ending: elapsed time is 00:00:05" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}