freedev_cycloneii_50.fit.qmsg

verilog 代码

{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_CANT_PACK_FAST_REGISTER_IO" "A\[0\] " "Warning: Can't pack node A\[0\] to I/O pin" { { "Warning" "WFSAC_FSAC_REGISTER_PACKING_NO_OUTPUT_IO_REGISTER_CONNECTION" "A\[0\] " "Warning: Can't pack node A\[0\] -- no packable connection between output pin and register" {  } { { "freedev_cycloneII_50_top.bdf" "" { Schematic "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50_top.bdf" { { 128 952 1128 144 "A\[24..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "A\[0\]" } } } } { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "" { A[0] } "NODE_NAME" } "" } } { "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.fld" "" { Floorplan "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.fld" "" "" { A[0] } "NODE_NAME" } }  } 0}  } { { "freedev_cycloneII_50_top.bdf" "" { Schematic "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50_top.bdf" { { 128 952 1128 144 "A\[24..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "A\[0\]" } } } } { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "" { A[0] } "NODE_NAME" } "" } } { "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.fld" "" { Floorplan "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.fld" "" "" { A[0] } "NODE_NAME" } }  } 2}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.30 0 1 0 " "Info: Number of I/O pins in group: 1 (unused VREF, 3.30 VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.30V 39 7 " "Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 39 total pin(s) used --  7 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.30V 15 28 " "Info: I/O bank number 2 does not use VREF pins and has 3.30V VCCIO pins. 15 total pin(s) used --  28 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.30V 1 38 " "Info: I/O bank number 3 does not use VREF pins and has 3.30V VCCIO pins. 1 total pin(s) used --  38 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 36 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  36 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use unused 0 44 " "Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  44 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use unused 2 41 " "Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  41 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use unused 0 36 " "Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  36 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use unused 1 38 " "Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  38 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Warning: Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "A\[25\] " "Warning: Node \"A\[25\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "A\[25\]" } } } }  } 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "BE\[0\] " "Warning: Node \"BE\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "BE\[0\]" } } } }  } 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "BE\[1\] " "Warning: Node \"BE\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "BE\[1\]" } } } }  } 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "NET_IRQ " "Warning: Node \"NET_IRQ\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "NET_IRQ" } } } }  } 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "NET_RST " "Warning: Node \"NET_RST\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "NET_RST" } } } }  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}