freedev_cycloneii_50.fit.summary

verilog 代码

Flow Status : Successful - Fri Aug 11 17:54:13 2006
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : freedev_cycloneII_50
Top-level Entity Name : freedev_cycloneII_50_top
Family : Cyclone II
Device : EP2C35F484C8
Timing Models : Preliminary
Met timing requirements : N/A
Total logic elements : 1,459 / 33,216 ( 4 % )
Total registers : 768
Total pins : 52 / 322 ( 16 % )
Total virtual pins : 0
Total memory bits : 169,984 / 483,840 ( 35 % )
Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )