📄 freedev_cycloneii_50.fit.rpt
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; freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle ; Duplicated ; Register Packing ; Fast Output Enable Register assignment ; REGOUT ; freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle~_Duplicate_14 ; REGOUT ;
; freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle ; Duplicated ; Register Packing ; Fast Output Enable Register assignment ; REGOUT ; freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle~_Duplicate_15 ; REGOUT ;
; freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_readn ; Packed Register ; Register Packing ; Fast Output Register assignment ; REGOUT ; FRD ; DATAIN ;
; freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|write_n_to_the_cfi_flash_0 ; Packed Register ; Register Packing ; Fast Output Register assignment ; REGOUT ; FWR ; DATAIN ;
; freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle~_Duplicate_1 ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; REGOUT ; D[14] ; OE ;
; freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle~_Duplicate_2 ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; REGOUT ; D[13] ; OE ;
; freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle~_Duplicate_3 ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; REGOUT ; D[12] ; OE ;
; freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle~_Duplicate_4 ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; REGOUT ; D[11] ; OE ;
; freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle~_Duplicate_5 ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; REGOUT ; D[10] ; OE ;
; freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle~_Duplicate_6 ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; REGOUT ; D[9] ; OE ;
; freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle~_Duplicate_7 ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; REGOUT ; D[8] ; OE ;
; freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle~_Duplicate_8 ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; REGOUT ; D[7] ; OE ;
; freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle~_Duplicate_9 ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; REGOUT ; D[6] ; OE ;
; freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle~_Duplicate_10 ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; REGOUT ; D[5] ; OE ;
; freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle~_Duplicate_11 ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; REGOUT ; D[4] ; OE ;
; freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle~_Duplicate_12 ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; REGOUT ; D[3] ; OE ;
; freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle~_Duplicate_13 ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; REGOUT ; D[2] ; OE ;
; freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle~_Duplicate_14 ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; REGOUT ; D[1] ; OE ;
; freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle~_Duplicate_15 ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; REGOUT ; D[0] ; OE ;
+--------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+------------------+----------------------------------------+-----------+--------------------------------------------------------------------------------------------------------------------------------------------+------------------+
+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.fit.eqn.
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.pin.
+--------------------------------------------------------------------------+
; Fitter Resource Usage Summary ;
+---------------------------------------------+----------------------------+
; Resource ; Usage ;
+---------------------------------------------+----------------------------+
; Total logic elements ; 1,459 / 33,216 ( 4 % ) ;
; -- Combinational with no register ; 751 ;
; -- Register only ; 78 ;
; -- Combinational with a register ; 630 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 639 ;
; -- 3 input functions ; 516 ;
; -- <=2 input functions ; 226 ;
; -- Register only ; 78 ;
; -- Combinational cells for routing ; 59 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 1216 ;
; -- arithmetic mode ; 165 ;
; ; ;
; Total registers ; 708 / 33,216 ( 2 % ) ;
; Total LABs ; 116 / 2,076 ( 5 % ) ;
; User inserted logic elements ; 0 ;
; Virtual pins ; 0 ;
; I/O pins ; 52 / 322 ( 16 % ) ;
; -- Clock pins ; 2 / 8 ( 25 % ) ;
; Global signals ; 8 ;
; M4Ks ; 46 / 105 ( 43 % ) ;
; Total memory bits ; 169,984 / 483,840 ( 35 % ) ;
; Total RAM block bits ; 211,968 / 483,840 ( 43 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % ) ;
; Global clocks ; 8 / 16 ( 50 % ) ;
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